On 03/27/2014 07:04 PM, rh_ wrote:
On Thu, 27 Mar 2014 16:25:29 -0500
David Lambert <d...@lambsys.com> wrote:
I have had a long and painful history using flash in general, and
have come to the conclusion that asynchronous removal of power is a
asynchronous? Like pulling the plug and not pushing it?
Yes.
very bad thing. The following link shows one low level phenomenon
called "unstable bits". This seems to be getting worse the more bits
that are stuffed into a cell (pretty obvious) :-[
low-level phenomenon? You mean a manufacturer defect? An inherent
defect in the flash design? Implementation defect?
All flash is inherently error prone. That's why long ECC codes are
employed as recommended by the flash chip manufacturers
Some other studies suggest that very high density chips may exhibit
similar problems even when *_reading_* during a power fail!
Ouch.
My conclusions lean to removing power only when ALL accesses to flash
have completed.
What technologies were used to reach your conclusion? Filesystems,
flash device, etc.
From the mid 1990s. Everything from raw NAND, NOR flash chips with ASIC
or software ECC controllers/wear leveling. USB/SD/CompactFlash. File
systems UBIFS, XFS, Ext2/3/4, FAT, and some proprietary sequential only
file systems with embedded EDC/ECC.
Why is this technology wide spread if it's got an inherent flaw?
Cheap, and with the right controllers, reliable.
Wikipedia has a good basic introduction to the technology with some more
authoritative citations. For greater depth some of the manufacturers'
data sheets may be helpful.
http://en.wikipedia.org/wiki/Flash_memory
http://www.micron.com/products/nand-flash
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