My dear Penguin,

Yes,  the desired SPS rate is rather low, as I was feeling limited by the
actual possibilities here. I am a pattern recognizer
bird myself, and looking primarily at 2 problems:
1. Non Invasive medical diagnostics. These use NIR, electronic noses, and
perhaps EEG, EMG.
2. The quantum mechanical nature of consciousness. These onvolve detecting
signals like 1 above - coupled with AI, like 1.

Both of these aims ask for rather many channels with rather low speeds.
Why? Because the combinatorial pattern recognizer asks for
a unique signature across many channels. Example (rough): Suppose you can
detect a signal in the NIR at .8 microns. It has 32 levels,
IOW a crappy signal. That's 2 exp 5. Now suppose you have 8 of these
channels. Suddenly, the degree of freedom is 2 exp 40. IOW
the signal is more unique, and noise has a harder time jamming.

That's the justification for many channels. Now, I wonder what your desire
for high speed is. What would you use it for? I looked at the
microchip pic24fj128gc010. That can do only 20 MSPS, though. (from memory)
OTOH, I have a Tektronix scope that can do 10 GSPS on 4 channels.
So I am not aware of ADC chips that fast - It's an interesting problem
though - How would you design such a thing?

Let's see - 120 MSPS would entail 240 MB/s at 16 bit res. (just for
argument here.). That seems well within SATA 3  and USB 3 type rates these
days.
But this is not a vanilla ADC chip.

A SAR-type design (speaking very roughly) will require 240x16x10exp6
comparisons per sec. That's a comparator speed of  4x10exp9 per sec -
A comparator can get a speed (realistically) of 10 nanosec. Thats 10 exp 8
comparisons per sec. So 4x10exp9/10exp8 = 40 comparators.

Seems doable, but I have shied away from it as being beyond my practicality
(and needs) - since I am not skilled in high speed circuit design, as well
as
the issue of handling and data storage at the CPU level.

I estimate that, in order to get that rate, you would have to build a desk
top super computer, made up of DSP board multiprocessors. (idea to get away
from
circuit design.)
Then the DSP memory would be connected to 1TB SSD drives to collect data.
At this rate, you are going to accumulate a gB in 4 seconds, so a 1TB SSD
will be good for
an hour of data collection.

What do you want this speed for? High speed events?
JB



On Sat, May 10, 2014 at 3:00 AM, sa_Penguin <[email protected]> wrote:

> 32 channels is - a lot. At 16-bit, too. On the other hand, the actual
> sample rate is quite low: 200K sample/sec
> This sounds like the backbone of a 32-channel audio mixing desk. Which is
> fine, if that's what you are into...
>
> Personally, I'd prefer 2 [or even 1] ADC channel, with a MUCH higher
> sample rate. Say: 120 M sample/sec.
> Sure there are faster ADC's - but original [parallel] ATA cables were
> rated to 133MHz, so I'm aiming for a spec
> that reduces the need for matching length tracks etc.
>
> You'd probably need an FPGA to interface that with a Beagleboard, or
> Beaglebone Black [my device].
>
> -- Alan
>
>
> On Wednesday, 12 May 2010 05:04:07 UTC+9:30, Ben Gamari wrote:
>>
>> Hey all,
>>
>> For those who care, I have drawn up designs for the second iteration of
>> my
>> BeagleBoard-based data acquisition platform[1].
>>
>> This new design features 32 DAC channels and 32 ADC channels, both with
>> 16-bit
>> resolution. The ADC sampling rate is a little lower than I would have
>> liked
>> at 100ksamples/second (with the SPI bus running at 2MHz), but this should
>> be
>> more than enough for most tasks. The DACs on the other hand can run at up
>> to
>> 20MHz (limited by the level shifters).  Additionally, the board now
>> exposes 8
>> GPIO pins behind a level shifter, making it possible to directly
>> interface with
>> standard 5V TTL levels.
>>
>> The ADC part I'm using is TI's ADS8344 and the DAC is TI's DAC8568. The
>> level
>> shifters are TI's TXB0108 and the demultiplexer used for chip select is
>> TI's
>> SN74AHC139. Altogether, the board is quite expensive. Each of the four
>> DACs are
>> $25.00 and each of the four ADCs are $10. Thus, a fully populated board
>> is
>> about $150 in parts alone. Far more expensive than I was hoping for, but
>> it
>> seems that these prices are pretty common in the world of converters.
>>
>> The board is designed to fit on a BeagleBoard XM-style expansion
>> connector and
>> thus sits beneath the BeagleBoard.
>>
>> One issue I encountered with the last design[2] was the large in-rush of
>> current at startup which seems to cause the BeagleBoard to brown-out.
>> This
>> makes it necessary to remove the board while starting up the BeagleBoard.
>> While
>> I'm not certain of the cause of this, I suspect that the largish filter
>> capacitors (330uF IIRC) on the voltage rails might be at least in part to
>> blame. Anyone have any thoughts on this?  I've reduced the value of these
>> to
>> 100uF, but it would be nice to have a slightly more certain solution.
>>
>> If anyone has any comments, I would love to hear them. I think this
>> design is
>> orders of magnitude better than the original, but there is no doubt still
>> room
>> for improvement. In particular, I would love to hear suggestions about
>> the PCB
>> layout. I took some steps to ensure good analog characteristics (e.g.
>> maintaining continuity in the ground plane), but I'm sure there are other
>> things that could be improved. Moreover, the reference supply is little
>> more
>> than a RC filter. Is this sufficient or could there be a better option
>> here
>> (perhaps an active voltage reference or Zener regulator)?
>>
>> Anyways, I look forward to hearing any feedback that folks have. Thanks
>> for
>> listening.
>>
>> Cheers,
>>
>> - Ben
>>
>>
>> [1] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq
>> [2] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq/Version1
>>
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