From: Kumar Abhishek <[email protected]>
Signed-off-by: Kumar Abhishek <[email protected]>
---
firmware/Makefile | 1 +
firmware/capes/BB-BEAGLELOGIC-00A0.dts | 257 +++++++++++++++++++++++++++++++++
2 files changed, 258 insertions(+)
create mode 100644 firmware/capes/BB-BEAGLELOGIC-00A0.dts
diff --git a/firmware/Makefile b/firmware/Makefile
index 80e03ac..8c070c7 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -183,6 +183,7 @@ fw-shipped-$(CONFIG_CAPE_BEAGLEBONE) += \
bone_pwm_P9_31-00A0.dtbo \
bone_pwm_P9_42-00A0.dtbo \
BB-BONE-PWMT-00A0.dtbo \
+ BB-BEAGLELOGIC-00A0.dtbo \
BB-BONE-PRU-01-00A0.dtbo \
BB-BONE-PRU-02-00A0.dtbo \
BB-BONE-PRU-03-00A0.dtbo \
diff --git a/firmware/capes/BB-BEAGLELOGIC-00A0.dts
b/firmware/capes/BB-BEAGLELOGIC-00A0.dts
new file mode 100644
index 0000000..089130b
--- /dev/null
+++ b/firmware/capes/BB-BEAGLELOGIC-00A0.dts
@@ -0,0 +1,257 @@
+/*
+ * This file is a part of the BeagleLogic Project
+ * Copyright (C) 2014 Kumar Abhishek
+ *
+ * Derived from the original works of Matt Ranostay and Pantelis Antoniou
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "ti,beaglebone", "ti,beaglebone-black",
"beaglelogic,beaglelogic";
+
+ /* Identification */
+ part-number = "bb-beaglelogic";
+ version = "00A0";
+
+ /* Resources for exclusive reservation */
+ exclusive-use =
+ // "P8.20", /* pru1: pr1_pru1_pru_r31_13 */
+ // "P8.21", /* pru1: pr1_pru1_pru_r31_12 */
+ "P8.27", /* pru1: pr1_pru1_pru_r31_8 */
+ "P8.28", /* pru1: pr1_pru1_pru_r31_10 */
+ "P8.29", /* pru1: pr1_pru1_pru_r31_9 */
+ "P8.30", /* pru1: pr1_pru1_pru_r31_11 */
+ "P8.39", /* pru1: pr1_pru1_pru_r31_6 */
+ "P8.40", /* pru1: pr1_pru1_pru_r31_7 */
+ "P8.41", /* pru1: pr1_pru1_pru_r31_4 */
+ "P8.42", /* pru1: pr1_pru1_pru_r31_5 */
+ "P8.43", /* pru1: pr1_pru1_pru_r31_2 */
+ "P8.44", /* pru1: pr1_pru1_pru_r31_3 */
+ "P8.45", /* pru1: pr1_pru1_pru_r31_0 */
+ "P8.46", /* pru1: pr1_pru1_pru_r31_1 */
+
+ /* The PRUs */
+ "pru0",
+ "pru1";
+
+ /* Pinmux Values */
+ fragment@0 {
+ target = <&am33xx_pinmux>;
+ __overlay__ {
+
+ pru_gpio_pins: pinmux_pru_gpio_pins {
+ pinctrl-single,pins = < >;
+ };
+
+ pru_pru_pins: pinmux_pru_pru_pins {
+ pinctrl-single,pins = <
+ // 0x084 0x2e /*
gpmc_csn2.pr1_pru1_pru_r30_13, MODE6 | INPUT | PRU */
+ // 0x080 0x2e /*
gpmc_csn1.pr1_pru1_pru_r30_12, MODE6 | INPUT | PRU */
+ 0x0ec 0x2e /*
lcd_ac_bias_en.pr1_pru1_r31_11, MODE6 | INPUT | PRU */
+ 0x0e8 0x2e /*
lcd_pclk.pr1_pru1_pru_r31_10, MODE6 | INPUT | PRU */
+ 0x0e0 0x2e /*
lcd_vsync.pr1_pru1_pru_r31_8, MODE6 | INPUT | PRU */
+ 0x0e4 0x2e /*
lcd_hsync.pr1_pru1_pru_r31_9, MODE6 | INPUT | PRU */
+ 0x0b8 0x2e /*
lcd_data6.pr1_pru1_pru_r31_6, MODE6 | INPUT | PRU */
+ 0x0bc 0x2e /*
lcd_data7.pr1_pru1_pru_r31_7, MODE6 | INPUT | PRU */
+ 0x0b0 0x2e /*
lcd_data4.pr1_pru1_pru_r31_4, MODE6 | INPUT | PRU */
+ 0x0b4 0x2e /*
lcd_data5.pr1_pru1_pru_r31_5, MODE6 | INPUT | PRU */
+ 0x0a8 0x2e /*
lcd_data2.pr1_pru1_pru_r31_2, MODE6 | INPUT | PRU */
+ 0x0ac 0x2e /*
lcd_data3.pr1_pru1_pru_r31_3, MODE6 | INPUT | PRU */
+ 0x0a0 0x2e /*
lcd_data0.pr1_pru1_pru_r31_0, MODE6 | INPUT | PRU */
+ 0x0a4 0x2e /*
lcd_data1.pr1_pru1_pru_r31_1, MODE6 | INPUT | PRU */
+ >;
+ };
+ };
+ };
+
+ /* PRU Configuration */
+ fragment@1 {
+ target = <&ocp>;
+
+ __overlay__ {
+
+ /* avoid stupid warning */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ prurproc {
+ compatible = "ti,pru-rproc";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pru_pru_pins>;
+
+ reg = <0x4a300000 0x080000>;
+
+ status = "okay";
+
+ ti,hwmods = "pruss";
+ ti,deassert-hard-reset = "pruss", "pruss";
+ interrupt-parent = <&intc>;
+
+ /* interrupts on the host */
+ interrupts = <20 21 22 23 24 25 26 27>;
+
+ /* events these interrupts map to (host
interrupt) */
+ events = <2 3 4 5 6 7 8 9>;
+
+ /* PRU interrupt controller offset */
+ pintc = <0x20000>;
+
+ /* 12K Shared Data RAM global, size, local */
+ pdram = <0x10000 0x03000 0x10000>;
+
+ /*
+ * SYSEVENT ids
+ *
+ * - PRU/ARM communication
+ * PRU0_PRU1 17
+ * PRU1_PRU0 18
+ * PRU0_ARM 19
+ * PRU1_ARM 20
+ * ARM_PRU0 21
+ * ARM_PRU1 22
+ *
+ * Full SYSEVENT list
+ *
+ * parity_err_intr_pend 0
+ * pru0_r31_status_cnt16 1
+ * pru1_r31_status_cnt16 2
+ * uart_urxevt_intr_req 4
+ * uart_utxevt_intr_req 5
+ * uart_uint_intr_req 6
+ * iep_tim_cap_cmp_pend 7
+ * ecap_intr_req 15
+ * pru_mst_intr[0-15]_intr_req 16-31
+ * nirq 32 (UART1)
+ * mcasp_x_intr_pend 33 (MCASP1)
+ * mcasp_r_intr_pend 34 (MCASP1)
+ * ecap_intr_intr_pend 35 (ECAP1)
+ * ecap_intr_intr_pend 36 (ECAP2)
+ * epwm_intr_intr_pend 37 (eHRPWM2)
+ * dcan_uerr 38 (DCAN0)
+ * dcan_int1 39 (DCAN0)
+ * dcan_intr 40 (DCAN0)
+ * POINTRPEND 41 (I2C0)
+ * ecap_intr_intr_pend 42 (ECAP0)
+ * epwm_intr_intr_pend 43 (eHRPWM0)
+ * SINTERRUPTN 44 (McSPI0)
+ * eqep_intr_intr_pend 45 (eQEP0)
+ * epwm_intr_intr_pend 46 (eHRPWM1)
+ * c0_misc_pend 47 3PGSW (GEMAC)
+ * c0_tx_pend 48 3PGSW (GEMAC)
+ * c0_rx_pend 49 3PGSW (GEMAC)
+ * c0_rx_thresh_pend 50 3PGSW (GEMAC)
+ * nirq 51 (UART0)
+ * nirq 52 (UART2)
+ * gen_intr_pend 53 (ADC_TSC)
+ * mcasp_r_intr_pend 54 (McASP0)
+ * mcasp_x_intr_pend 55 (McASP1)
+ * pwm_trip_zone 56
(eHRPWM0/eHRPWM1/eHRP WM2)
+ * POINTRPEND1 57 (GPIO0)
+ * Emulation Suspend Signal 58 (Debugss)
+ * initiator_sinterrupt_q_n2 59 (Mbox0 -
mail_u2_irq (mailbox interrupt for pru1))
+ * initiator_sinterrupt_q_n1 60 (Mbox0 -
mail_u1_irq (mailbox interrupt for pru0))
+ * tptc_erint_pend_po 61 (TPTC0
(EDMA))
+ * tpcc_errint_pend_po 62 (TPCC (EDMA))
+ * tpcc_int_pend_po1 63 (TPCC (EDMA))
+ *
+ * HOST interrupt ids
+ *
+ * PRU0 0
+ * PRU1 1
+ * EVTOUT0-7 2-9
+ */
+
+ /* sysevent map to intc channel */
+ sysevent-to-channel-map =
+ <17 1>, /* PRU0_PRU1 -> CH1 */
+ <18 0>, /* PRU1_PRU0 -> CH0 */
+ <19 2>, /* PRU0_ARM -> CH2 */
+ <20 3>, /* PRU1_ARM -> CH3 */
+ <21 0>, /* ARM_PRU0 -> CH0 */
+ <22 1>, /* ARM_PRU1 -> CH1 */
+ <24 4>, /* VRING Host->PRU0 -> CH4 */
+ <25 5>, /* VRING PRU0->Host -> CH5 */
+ <26 6>, /* VRING Host->PRU1 -> CH6 */
+ <27 7>; /* VRING PRU1->Host -> CH7 */
+
+ /* channel to host interrupt map */
+ channel-to-host-interrupt-map =
+ <0 0>, /* CH0 -> PRU0 */
+ <1 1>, /* CH1 -> PRU1 */
+ <2 2>, /* CH2 -> EVTOUT0 */
+ <3 3>, /* CH3 -> EVTOUT1 */
+ <4 0>, /* CH4 -> PRU0 */
+ <5 6>, /* CH5 -> EVTOUT4 */
+ <6 1>, /* CH6 -> PRU1 */
+ <7 7>; /* CH7 -> EVTOUT5 */
+
+ /* indices are ARM=0, PRU0=1, PRU1=2 */
+ target-to-sysevent-map =
+ <0xffffffff 21 22>,
/* ARM: DONTCARE, ARM_PRU0, ARM_PRU1 */
+ < 19 0xffffffff 17>,
/* PRU0: PRU0_ARM, DONTCARE, PRU0_PRU1 */
+ < 20 18 0xffffffff>;
/* PRU1: PRU1_ARM, PRU1_PRU0, DONTCARE */
+
+ /* both the PRUs have 200MHz frequency so
period is 5ns */
+ clock-freq = <200000000>;
+
+ /* Enable BeagleLogic extensions to the rproc
driver */
+ pru-beaglelogic-enabled;
+
+ /* Add default settings for the LA core */
+ pru-beaglelogic {
+ compatible = "beaglelogic,beaglelogic";
+ samplerate = <50000000>; /*
100MHz, 50MHz, 40MHz, 25MHz, 20MHz, 10MHz, 5MHz, 1MHz : (200 / int n) MHz */
+ sampleunit = <1>; /*
Sample byte count: 1 or 2 bytes */
+ triggerflags = <0>; /* RFU
for further firmware revisions */
+ };
+
+ /* PRU0 - psuedo-DMA controller */
+ pru0 {
+ pru-index = <0>;
+
+ /* offset, size, local */
+ iram = <0x34000 0x02000 0x00000>;
/* code ram (8K) */
+
+ /* offset, size, local, other */
+ dram = <0x00000 0x02000 0x00000
0x10000>; /* data ram (8K) */
+
+ pctrl = <0x22000>;
+ pdbg = <0x22400>;
+
+ /* sysevents signaling ring activity
(host, pru)*/
+ vring-sysev = <24 25>;
+
+ firmware-elf;
+ firmware = "beaglelogic-pru0";
+ };
+
+ /* PRU1 - data capture */
+ pru1 {
+ pru-index = <1>;
+
+ /* offset, size, local */
+ iram = <0x38000 0x02000 0x00000>;
/* code ram (8K) */
+
+ /* offset, size, local, other */
+ dram = <0x02000 0x02000 0x00000
0x10000>; /* data ram (8K) */
+
+ pctrl = <0x24000>;
+ pdbg = <0x24400>;
+
+ /* sysevents signaling ring activity
(host, pru)*/
+ vring-sysev = <26 27>;
+
+ firmware-elf;
+ firmware = "beaglelogic-pru1";
+ };
+ };
+ };
+ };
+};
--
1.9.1
--
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