Hi, John, could you specify which 1MHz timer ? I just know 24MHz clock for ADC... About synchronization, I will try to synchronize ADC(with PRU as Lenny said) to PTP clock (on CPTS, common platform time sync) rather than kernel system clock. Do you have experience handling CPTS? I am not sure if CPTS driver has ability of triggering other hardware unit (software trigger), and what its accuracy of synchronization is.
Thanks. john3909於 2014年7月24日星期四UTC+8上午1時43分56秒寫道： > > > From: Lenny <[email protected] <javascript:>> > Reply-To: "[email protected] <javascript:>" < > [email protected] <javascript:>> > Date: Wednesday, July 23, 2014 at 10:29 AM > To: "[email protected] <javascript:>" <[email protected] > <javascript:>> > Cc: <[email protected] <javascript:>> > Subject: [beagleboard] Re: How to synchronize ADC sampling clock ？ > > Hi, > > if you control the ADC from the PRU, you can use the ADC in > single-acquisition mode and perform a new acquisition every 200 PRU cycles > (every microsecond) for example (or whatever repetition rate you want), and > therefore use the 200 MHz PRU clock as a low-jitter timer. This way you can > have jitter values well below one microsecond. You should also be able to > synchronize the PRU with an external clock on one of its input pins leading > to the r31 register if that is still needed. > > There should probably be a residual timing jitter of maximally 1/24MHz > (ca. 42ns) because (as far as i know, but im not sure) the 24 MHz ADC > sampling clock is not intrinsically synchronized with the 200 MHz PRU > clock, so once the PRU launches a new acquisition, it won't take place > before the ADC clock starts a new cycle. I did not find any documentation > on how the PRU and ADC clock signals are derived in the hardware, that is > if they come from the master clock or not, but i did experimentally observe > a jitter of a few percent of a microsecond. > > If you want I can send you some code examples. > > That sounds like a good solutions. Also, you could use a 1MHz timer which > you can synchronize to the PTP clock and then just average the ADC samples > received since the last clock interrupt. > > Regards, > John > > > > Lenny > > > > On Tuesday, July 22, 2014 8:08:39 AM UTC+2, [email protected] wrote: >> >> Hi, >> how to synchronize ADC sampling clock (CLK_M_OSC, in AM335x manual, page >> 3731) with external 1PPS source or others? >> I used PTP to synchronize system clock in the kernel before, however, the >> jitter is about 30us （but I need a jitter with accuracy under 1us.）. >> So I want to synchronize ADC sampling clock(24MHz), Is there any way to >> synchronize it ? Is the clock of CLK_M_OSC be adjustable? >> Thanks. >> > -- > For more options, visit http://beagleboard.org/discuss > --- > You received this message because you are subscribed to the Google Groups > "BeagleBoard" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected] <javascript:>. > For more options, visit https://groups.google.com/d/optout. > > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
