Hi
I've notice a couple of threads that talk about people using the RMII
interface
and there being some issues. However, I haven't seen any resolutions posted.
I have gotten the interface to do the negotiation for link and speed.
This all seems to happen over the MDIO interface.
When it gets to DHCP - it times out.
I don't see any traffic over the RX or TX lanes of the RMII interface
and I don't see any packet requests via Wireshark.
However, there is a lot of traffic over the MDIO interface while waiting
for time out.
I can only infer on this that I am missing something in the software side
of the setup.
I am working in CE7, but would welcome any feedback from the Linux or
other OS folks as it will likely be applicable just not identical.
I've gone through this as far as a hardware guy knows how. I could use
some pointers from the software people out there.
Things that I know needed to be done:
Set GMII_SEL_REG to 0xF5
this sets the reference clocks to inputs from the phys
also sets the ports to RMII mode vs MII or RGMII.
Set pad configs to:
PAD_ENTRY(MII1_RXERR, MODE(1) | RXACTIVE)
/* RMII1_RXERR (J15)i - RMII1_RXERR */ \
PAD_ENTRY(MII1_TXEN, MODE(1)) /*
RMII1_TXEN (J16)o - RMII1_TX_EN */ \
PAD_ENTRY(MII1_CRS, MODE(1) | RXACTIVE)
/* RMII1_CRS_DV (H17)i - RMII1_CRS_DV */ \
PAD_ENTRY(MII1_TXD1, MODE(1)) /*
RMII1_TXD1 (K16)o - RMII1_TXD1 */ \
PAD_ENTRY(MII1_TXD0, MODE(1)) /*
RMII1_TXD0 (K17)o - RMII1_TXD0 */ \
PAD_ENTRY(RMII1_REFCLK, MODE(0) | RXACTIVE) /* RMII1_RXCLK (H18)i -
RMII1_REFCLK */ \
PAD_ENTRY(MII1_RXD1, MODE(1) | RXACTIVE)
/* RMII1_RXD1 (L15)i - RMII1_RXD1 */ \
PAD_ENTRY(MII1_RXD0, MODE(1) | RXACTIVE)
/* RMII1_RXD0 (M16)i - RMII1_RXD0 */ \
PAD_ENTRY(GPMC_WPN, MODE(3) | RXACTIVE) /* RMII2_RXERR (U17)i -
RMII2_RXERR */ \
PAD_ENTRY(GPMC_A0, MODE(3)) /* RMII2_TXEN (R13)o - RMII2_TXEN
*/ \
PAD_ENTRY(GPMC_WAIT0, MODE(3) | RXACTIVE) /* RMII2_CRS_DV (T17)i -
RMII2_CRS_DV */ \
PAD_ENTRY(GPMC_A4, MODE(3)) /* RMII2_TXD1 (R14)o - RMII2_TXD1
*/ \
PAD_ENTRY(GPMC_A5, MODE(3)) /* RMII2_TXD0 (V15)o - RMII2_TXD0
*/ \
PAD_ENTRY(MII1_COL, MODE(1) | RXACTIVE) /* RMII2_RXCLK (H16)i -
RMII2_REFCLK */ \
PAD_ENTRY(GPMC_A10, MODE(3) | RXACTIVE) /* RMII2_RXD1 (T16)i -
RMII2_RXD1 */ \
PAD_ENTRY(GPMC_A11, MODE(3) | RXACTIVE) /* RMII2_RXD0 (V17)i -
RMII2_RXD0 */ \
PAD_ENTRY(MDIO_DATA, MODE(0) | RXACTIVE | PULLUP_EN) /* MDIO_DATA
*/ \
PAD_ENTRY(MDIO_CLK, MODE(0) | PULLUP_EN) /*
MDIO_CLK */ \
If anyone see something I did wrong or knows of additional things I need to
do, I'd appreciate the insight.
Thanks,
Matt
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