The CPU ball mapping is hard coded in the AM335x logic, no tricks AFAIK. Your list seems to be OK (I didn't check all details). There're just a few header pins usable for PRUSS low latency GPIO, when LCD isn't disabled. All other GPIOs can get accessed over the OCP master port with 2 or 3 cycles of latency.
Instead of memory mapped access (from the host) I recommend to consider controlling the GPIO subsystems directly by the PRU. Find some example code in the package libpruio <http://beagleboard.org/project/libpruio/>. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
