On 1/19/2015 11:44 AM, Bill Gray wrote:
> 
> BUT... you say that the read-modfiy-write sequence will not be atomic?
> This is the part of the setup that is run by the PRU.  If this is not
> atomic, am I correct in understanding that my PRU program loop will no
> longer run on a predictable frequency?  I suppose I can tolerate timing
> chaos of 20-30ns, but not much more than that... and I would prefer to have
> my PRU loop running very regularly!
> 
> Have I understood you correctly?

Each of the memory writes will be atomic, but since you have two things
writing to the same memory location, the PRU might miss one of the ARM
code writes (or the ARM might miss the PRU write, depending on exactly
what you're doing).  It's generally safer to have only one process write
each memory location and use an appropriate handshake mechanism.

This is "real-time 101", and there are a *LOT* of different ways to
handle synchronization, but one example of what you could do is:

* PRU updates a value (ie: adds one, changes a pointer to data, etc.)

* ARM reads the value and notices it changed (by comparing it to the
last value read)

* ARM core does whatever is needed, then writes a new value into a
*DIFFERENT* spot in the PRU memory.  This could be the same value
written by the PRU or some other value, depending on what you're doing

* The PRU monitors the second memory location (written by the ARM) and
when it changes, the PRU knows the ARM has completed it's task.

* ...wait for the PRU to trigger the process again...

There are many lock-free semaphore, fifo, and synchronization mechanisms
you can use to safely communicate between the two asynchronous CPUs
(ARM+PRU).  Google a bit and/or provide more application details if the
above mechanism doesn't sound like what you need.

-- 
Charles Steinkuehler
[email protected]

-- 
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