Hello all Do you know , how to enable L2 cache in Beagle-x15 board ?
Searching from google , and linux kernel source . I dont find any function about the scu config for enable in kernel . For Cortex-A9 , there will be almost PL310 cache controler , but on Cortex A15 ,intergrated SCU replace the PL310 . But I dont find any code related . Does anyone know about this ? Any idea is welcome and appreciate Thanks and regards -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
