Hello, I'm looking for inputs/ideas regarding the potential power-down issue of the BBB, which is believed to cause HW failure when the 5V is suddenly interrupted without shutting down the PMIC first. New BBBs come with warnings saying that the board has to be shut-down by SW to avoid HW failure. My thought was the following (assuming no battery connected): 1) when the 5Vin goes down (suddenly, without glitches), the UVLO detects this at around 3.5V (UVLO level of 3.3V + "offset" spec of 200mV), and "immediately" does the next 2 things. 2) the UVLO event brings down the PMIC_PGOOD signal, which generates a reset (PORZ) in the processor that turns all the clocks off (dramatically reducing the current consumption). 3) the UVLO event starts the power-down sequence that should last a few miliseconds. Since there is some capacitance (100uF) in SYS_5V, that energy reserve "may" be enough to let the PMIC finish the power down sequence. It's very little energy and the UVLO level is pretty low, so this energy would be useful only if the power consumption is really low (which I hope because of step 2). If any of these steps is not consistently happening every time, then that may be the key to solve the issue. What do you think about this logic? do you think those 3 steps happen? My plan is to put scope probes in all the voltage rails to capture how far it is from completing the power down sequence under this circumstance. But the more I know in advance about the issue the better I will be to analyze it. Regards, Max PS: I had posted this issue in the Beaglebone group but it isn't very popular... I apologize that I had to re-post it here.
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