There is not an issue here. This is just Paul's opinion. He has lots of opinions.
Gerald On Wed, May 13, 2015 at 1:17 PM, Mikhail < [email protected]> wrote: > Here is the relevant answer from TI: > > https://e2e.ti.com/support/arm/sitara_arm/f/791/p/422733/1508580#1508580 > > TI is suggesting that there is still a bug on BBB PCB: > "Note: The BeagleBone Black should have a resistor in series with the > AM335x WARMRSTn terminal (named NRESET_INOUT on BeagleBone Black schematic > symbol) to limit the current when these two outputs are driven to opposite > logic levels. Without the series resistor, the output of U16 could be > driven low while the WARMRSTn terminal is driven high for a short duration > as power is sequenced. You may not need this circuit if the components > connected to the WARMRSTn output do not have an issue with a short duration > high level pulse driven from WARMRSTn." > > > > > > On Friday, May 8, 2015 at 1:17:22 PM UTC-4, Mikhail wrote: >> >> >> Hello, >> >> We are building a custom board, based on BBB. We are looking at the >> following revisions that look different from the official AM335x-evm design: >> >> Rev A6A: 3) "Changed C24 to a 2.2uF capacitor. This extends the reset >> signal to solve an issue where some boards would not boot on power up." >> >> In our custom board, we use nRESETin_out as output to reset external >> peripherals, and having this larger cap prevents the line from going low >> during warm reset, as per this TI forum post: >> https://e2e.ti.com/support/arm/sitara_arm/f/791/p/299818/1047664#1047664 >> Our custom board will not use a nRESETin_out with a push button, >> therefore, do we still need it, and if yes, how does adding this capacitor >> improve sitara processor boot success on POR? >> >> Rev A6: 1) "Based on notification from TI, in random instances there >> could be a glitch in the SYS_RESETn signal from the processor where the >> SYS_RESETn signal was taken high for a momentary amount of time before it >> was supposed to. To prevent this, the signal was ORed with the PORZn (Power >> On reset)." >> >> What subsystems/peripherals were impacted by this glitch? We suspect >> that this change relates to having to satisfy the 25ms nRST requirement >> of the LAN8710A PHY. We are thinking of using an alternative approach, by >> using GPIO to drive nRST pin of LAN8710A, as suggested on TI forums: >> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/347189. In which case, >> do we still need this fix ? >> >> >> Regards, >> Mikhail >> > -- > For more options, visit http://beagleboard.org/discuss > --- > You received this message because you are subscribed to the Google Groups > "BeagleBoard" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- Gerald [email protected] http://beagleboard.org/ http://circuitco.com/support/ -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
