Completely understood; however, assuming one could meet board area and 
timing constraints, it might be possible to wrap the processor with a 
circuit prophylactic, as it were...

I've also been part of several ARM-based core silicon projects, and it 
would have been possible for that (i.e. consistent pre-reset I/O state) to 
have been addressed at the chip level.

Mike

On Tuesday, September 8, 2015 at 5:56:32 AM UTC-6, Gerald wrote:
>
> I/O pin functionality is a function of the processor. Not the board.
>
> Gerald
>
> On Mon, Sep 7, 2015 at 10:05 PM, rattus <[email protected] <javascript:>> 
> wrote:
>
>> On Monday, September 7, 2015 at 6:52:12 PM UTC-6, Graham wrote:
>>>
>>> Well, by definition, the boot programming pins are going to have the 
>>> pull-ups / pull-downs, so you know what they are going to be doing, until 
>>> over-ridden.
>>>
>>> Most processors start up with the programmable pins as inputs, then move 
>>> to the configured state.
>>>
>>
>> If it were so... but it seems with such an abundance of modes and pins, a 
>> number of the pins I am using are in a variety if input, output, hi-Z and 
>> I/O defaults at powerup, most often with pullup or pull-downs. The good 
>> news is, I've added enough gating and the additional fast-starting Vdd to 
>> avoid conflicts. SPI attached peripherals (powered early) all need commands 
>> shifted in to drive outputs, so that's safe too.
>>
>> Now for the *next* Beaglebone, innocuous I/Os would be a great feature...
>>
>> Anything else can be dangerous to the pins.  But, as Charles says, RTFM.
>>>
>>
>>> If you are concerned, use the bus-isolation /transmission-gate  chips, 
>>> power them early, supply your own pull-ups/pull-downs, and switch the 
>>> connection on when SYS_RESETn goes high.  Then you are unconditionally 
>>> safe, and in-control.
>>>
>>> --- Graham
>>>
>>
>> Thanks, 
>>
>> Mike 
>>
>

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