Chandan,
1) Signals in banks may be swapped to aid in routing - this will in no way
affect operation.
If you cross banks then it will likely not work.
2) If the two are DDR3 and speed rated the same, the JEDEC std should make
them compatible.
However, check the datasheets carefully to be sure.
3) See #2 - shouldn't need to unless the datasheets show a difference.
4) Did you run any signal integrity analysis on your layout / design?
Termination can vary based on layout. But likely shouldn't need to be
changed from the ref.
I'd suspect your layout has some issues.
Try clocking down the interface to see if you can run at lower speeds.
If not, double check your design and make sure all is correct hw & sw.
I'm sure you'll find something is not correct.
Good Luck,
Matt
On Tuesday, February 16, 2016 at 8:09:12 AM UTC-6, Chandan Kumar wrote:
>
> Hi Sir,
>
> We have designed a PCB with AM5728 processor,and we have kept beagle bone
> X15 schema as reference.
>
> In Beagle board X15 schematics, in DDR3 section the data lines are not
> connected in straight forward way(i mean data line 15 of ddr3 is given to
> data line 10 of AM5728 and similarly in the same way for few other data
> lines.Please answer me the following questions
>
> 1)Please provide me the purpose for connecting the DDR3 in the above said
> way.
>
> 2)In beagle board X15 kingston make DDR3(D2516EC4BXGGB) is used and we
> have used micron chip(MT41K256M16HA-125 :IT) .
>
> The schema for DDR3 is same as beagle board X15.
>
> 3)Do we need to change any configurations for using micron chip in the
> kernel
>
> 4)Do we need to change the value of termination resistors used
>
>
> Please answer the above questions as we have presently struck in uboot
> level and there is problem in starting with the kernal
>
> Thanks,
> Chandan
>
>
>
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