Hi, guy.
I had had the same problem.
But I solved it.
The problem was very simple.
We have to set "RXACTIVE" bit to CLK Pin's "Conrol Module Resiters(PINMUX)".
So dts file is follows
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (P23)
spi0_sclk.spi0_sclk */
0x154 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T22) spi0_d0.spi0_d0
*/
0x158 ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (T21)
spi0_d1.spi0_d1 */
0x15c ( PIN_OUTPUT_PULLUP | MUX_MODE0 ) /* (T20)
spi0_cs0.spi0_cs0 */
>;
};
And, we can see in "Technical Reference Manual" 26.2.3.
It is said "SPI serial clock (output when master, input when slave)"
And it also said "(1) This output signal is also *used as a re-timing input*.
The associated CONF_<module>_<pin>_RXACTIVE bit for the* output clock must
be set to 1 to enable the clock input back* to the module."
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