>
> Le mercredi 18 mai 2016 00:04:16 UTC+2, Charles Steinkuehler a écrit :
> The modifications you made to the code to support two channels are
> just wrong, you need to set/clear both output data bits before setting
> the clock pin high. Also, you'll use far fewer cycles if you can
> manage to shift out bytes or words instead of single bits, but that
> will depend on how you have the PRU I/O pinned out and if you can
> tolerate the extra overhead in the ARM to PRU communications.
>
> --
> Charles Steinkuehler
> [email protected]
Hi Charles,
first thanks for your answer.
Then, I tried to follow your idea, I have change the code to the following
SEQCLK:
MOV r0, DELAY_HIGH // time for clock low -- assuming clock low
before cycle
CLKLOW:
SUB r0, r0, 1 // decrement the counter by 1 and loop (next line)
QBNE CLKLOW, r0, 0 // check if the count is still low
//for OUT_1
QBBC DATALOW_1, REGISTER_OUT_1.t31 // The write state needs to be set
right here -- bit 31 shifted left
SET DATA_OUT_1
SET DATA_OUT_2
QBA DATACONTD
DATALOW_1:
CLR DATA_OUT_1
CLR DATA_OUT_2
DATACONTD:
SET PIN_CLK // set the clock high
MOV r0, DELAY_LOW // time for clock high
CLKHIGH:
SUB r0, r0, 1 // decrement the counter by 1 and loop (next line)
QBNE CLKHIGH, r0, 0 // check the count
LSL REGISTER_OUT_1, REGISTER_OUT_1, 1 //shift left the data
LSL REGISTER_OUT_2, REGISTER_OUT_2, 1 //shift left the data
// clock goes low now
CLR PIN_CLK // set the clock low
DATAINLOW:
RET
-> Lead that I observed the data of Out_1 on both OUT (1 and 2), however,
it doesn't sound right for me because, we don't check the
REGISTER_OUT_2.t31,
and it didn't allow me to send two different data.
I have also tried
SEQCLK:
MOV r0, DELAY_HIGH // time for clock low -- assuming clock low
before cycle
CLKLOW:
SUB r0, r0, 1 // decrement the counter by 1 and loop (next line)
QBNE CLKLOW, r0, 0 // check if the count is still low
QBBC DATALOW_1, REGISTER_OUT_1.t31 // The write state needs to be set
right here -- bit 31 shifted left
SET DATA_OUT_1
QBBC DATALOW_2, REGISTER_OUT_2.t31 // The write state needs to be set
right here -- bit 31 shifted left
SET DATA_OUT_2
QBA DATACONTD
DATALOW_1:
CLR DATA_OUT_1
QBBC DATALOW_2, REGISTER_OUT_2.t31 // The write state needs to be set
right here -- bit 31 shifted left
SET DATA_OUT_2
QBA DATACONTD
DATALOW_2:
CLR DATA_OUT_2
DATACONTD:
SET PIN_CLK // set the clock high
MOV r0, DELAY_LOW // time for clock high
CLKHIGH:
SUB r0, r0, 1 // decrement the counter by 1 and loop (next line)
QBNE CLKHIGH, r0, 0 // check the count
LSL REGISTER_OUT_1, REGISTER_OUT_1, 1 //shift left the data
LSL REGISTER_OUT_2, REGISTER_OUT_2, 1 //shift left the data
// clock goes low now
CLR PIN_CLK // set the clock low
DATAINLOW:
RET
Which normally check REGISTER_OUT_1 and 2 and also set/clear both output
data bits before setting
the clock pin high. Nevertheless, it led that I still doesn't observe any
signal on OUT_2.
So, are my ideas in the good direction, if so what can I improve, else what
is still wrong ?
For the part of trying to shift out bytes or words instead of single bits,
I was guessing that it was linked to LSL command,
If I change it by
LSL REGISTER_OUT_1, REGISTER_OUT_1, 2 //shift left the data
LSL REGISTER_OUT_2, REGISTER_OUT_2, 2 //shift left the data
It's lead to the same result as
LSL REGISTER_OUT_1, REGISTER_OUT_1, 2 //shift left the data
LSL REGISTER_OUT_2, REGISTER_OUT_2, 1 //shift left the data
i.e. the two data are the same and it is one out of two bits.
So is it the idea to shift out more bits at the same time, or is it
completely something else ?
Thanks by advance
Regards
Vincent
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