Hi! Are you talking about the PHYs? The normal way should be (as far as I understand) to cede the reset-timing to the prueth driver. But if I do so (define reset-gpios and reset-delay-us in pruss-mdio node), the PHY reset is never released. So I handle the PHY-reset manually via GPIO access within a script. (The same script works fine if I use the PRU ports with EtherCAT or ProfiNet firmware)
Btw. the CPSW ethernet port (eth0) works fine, if I didn't mention it clearly enough. Am Sonntag, 18. Dezember 2016 03:34:29 UTC+1 schrieb c2h2: > > Hi, are the power sequence /reset timing on the 3 ports correct? > > On Fri, Dec 16, 2016 at 3:50 PM, Daniel Gorsulowski < > [email protected] <javascript:>> wrote: > >> Hi! >> >> I have an issue with a custom board, based on BeagleBone Black (BEAGLEBK) >> and AM3359 ICS (TMDSICE3359) design. >> ... >> > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/0b43b341-3941-4a4b-b922-22da28778787%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
