On 2/9/2017 7:37 PM, William Hermans wrote: > However, the 8k memory used by each PRU core, as well as the shared 12k > memory > each PRU has access to is supposed to be single cycle read / write access. In > fact each PRU core as I understand it has the ability to "broadside" all of > it's > 32bit registers in a single cycle over to the 12k shared memory.
You cannot "broadside" store the register file into the 8k or 12k data rams, only into one of the three scratch pad locations or directly into the other PRU's register file. Table 4-21 (of the AM335x TRM version spruh73o) lists what happens when you encounter collisions or stalls with the XIN/XOUT commands. -- Charles Steinkuehler [email protected] -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/ac968e7e-03be-f91f-e47b-0476c7f777ee%40steinkuehler.net. For more options, visit https://groups.google.com/d/optout.
