The overlay for the SPI0 interface includes the following lines
pinctrl-single,pins = <
0x150 0x30 /* spi0_sclk, INPUT_PULLUP | MODE0 */
0x154 0x30 /* spi0_d0, INPUT_PULLUP | MODE0 */
0x158 0x10 /* spi0_d1, OUTPUT_PULLUP | MODE0 */
0x15c 0x10 /* spi0_cs0, OUTPUT_PULLUP | MODE0 */
>;
Notice the first line, which specifies that the spi0 clock signal is an
input with a pullup enabled.
This does not make sense to me, since every diagram I have seen (for
example in Derek Molloy's
book, Exploring Beaglebone) shows the clock signal as an *output* from the
BeagleBone. I have checked
the BeagleBone schematic and the processor pin for this signal connects
only to the P9 header.
So the only way it would make sense for this pin to be an input is if the
user is expected to have
a clock generation circuit on the cape. It's hard for me to imagine that
this is the intended usage.
I have seen this same configuration for the overlay in multiple places, so
I am guessing it is
correct, but I cannot understand why. Can someone knowledgable out there
please enlighten me?
Thanks,
Jon Turner
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