Charles, thanks very much for the quick reply. I've tried the following two assembly language programs based on your suggestion:
.origin 0 .entrypoint start start: wbs r31, 16 ldi r30, 0 wbc r31, 16 ldi r30, 0xff jmp start and .origin 0 .entrypoint start start: mov r2, 0 mov r3, 0xff wait_one_to_zero: qbbs wait_one_to_zero, r31, 16 mov r30, r2 wait_zero_to_one: qbbc wait_zero_to_one, r31, 16 mov r30, r3 jmp wait_one_to_zero Both programs still have the 25ns delay between the clock edge on R31 and the change in the R30 transitions. This seems to indicate that I'm looking at a 2 clock cycle delay for the commands and a ~3 clock cycle combined latency on the input and output pins. Probably some kind of buffering or latching delay. Too bad they don't mention this in the reference manual. Fig. 4.8 in Section 4.4.1.2.3.1 is a bit misleading. -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/8804e89a-8c53-4d95-9bdf-3abcd1c38ec6%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
