First, a lot of thanks for the pointer, that could really help.
What I really want to accomplish is to get at least a medium bandwidth
interface
between the LAN and some real-time data aquisition units. The LAN side is
patterned after my Agilent 89441A vector signal analyzer. You simply open
port 5025 on 192.169.178.111 and dump/read there GPIB/IEEE488-like
commands &
data streams. That side seems to work, although there is not yet much flesh
to it since the data collection side is still missing.
First I wanted to try the SPI interface, then the 16 bit multiplexed bus
to get an intelligent register interface to some FPGA.
For the SPI, I decided to attach a LT2500-32 ADC; that can do 1 Msample
at 24 bits. Add FFTW in the BBB and you have a respectable Fourier analyzer.
For the hardware, that's all that is needed:
<
https://www.flickr.com/photos/137684711@N07/45331444582/in/album-72157662535945536/
>
The Xilinx Coolrunner2 generates the sampling clock from the 100 MHz
crystal osc. and collects
some left-over gates. $1.50 or so. The other small board is the ADC, its
regulators and reference.
Home-etched and soldered. :-) It's completely open, in case someone
wants it.
The SPI has soaked up much more time than I had planned. A new Debian
image from
Robert and some other insights at least made that I don't get a bus
error for each SPI access.
One gets thankful for small advances... At least I can now create and
start PRU programs,
talk to them via the shared RAM and transfer huge data blocks to Linux
virtual memory land
through ping-pong buffers. It's just that I can't make the SPI say a
word. Verbatim. :-(
I also can finger the SPI pins when I re-assign them to the PRU and use
R30/R31.
I also have a Red Pitaya. I like it architecture-wise, except that I'll
need a larger FPGA
to support fast ADCs with JESDI204B ports - and that it is based on that
exotic Alpine Linux.
FPGAs are a home game for me, I've used them since there has been Xilinx.
best regards,
Gerhard
Am 17.10.2018 um 04:43 schrieb John Syne:
BTW, you mentioned moving to Zynq, but that processor is more
expensive than the complete BBB. Zynq eval boards or kits are even
more expensive, not to mention the cost of tools, etc. One other
problem is the learning curve is very steep if you want to take
advantage of the FPGA features. Anyway, the applications for Zynq and
BBB are completely different. I know, because I have looked at the
possibility of using Zynq over the years and each time, I have given
it a pass.
I’m currently using PSOC6 (CortexM4 and CortexM0) for some of my
projects (no Linux, using FreeRTOS) and it has a Verilog programmable
frontend, which is much easier to learn.
Regards,
John
--
For more options, visit http://beagleboard.org/discuss
---
You received this message because you are subscribed to the Google Groups "BeagleBoard" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
To view this discussion on the web visit
https://groups.google.com/d/msgid/beagleboard/09d5304e-5642-0db2-7755-596ee4ccb1a4%40hoffmann-hochfrequenz.de.
For more options, visit https://groups.google.com/d/optout.
