I have utilized the TI PinMux tool to create all of the necessary functions
that I need in my project.
I just cannot seem to get past how to create the .dtb file from the output
of the PinMux tool. I have a handful of files that are C defines and such,
but no clear path to the dts or dtb file.
I have spend hours looking, and running scripts and pulling down git repos,
to find that "my build" which is just the downloaded SDK SDcard image of
the Matrix build from TI...
All of the links to the Cloud9 distro are not
working, https://github.com/beagleboard/BeagleBoard-DeviceTrees.git for
example is not something that works at all. The four files that I have
here are ones that are perhaps what I need to use, but I just don't know
where to start.
Thanks in advance.
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/* PinMux automatically generated generic format file dump. */
/* register_address(hex) a_delay(decimal) g_delay(decimal)
register_name(string) ball_name(string) */
0x4844AA58 0 1900 CFG_VIN2A_D10_OUT D3
0x4844AA70 0 3400 CFG_VIN2A_D12_OUT D5
0x4844AA7C 0 3200 CFG_VIN2A_D13_OUT C2
0x4844AAAC 0 3000 CFG_VIN2A_D17_OUT D6
0x4844AAB8 0 2200 CFG_VIN2A_D18_OUT C5
0x4844AADC 0 1800 CFG_VIN2A_D20_OUT B3
0x4844AAE8 0 1900 CFG_VIN2A_D21_OUT B4
0x4844AA80 0 0 CFG_VIN2A_D14_IN C3
0x4844ACF8 0 1600 CFG_XREF_CLK0_OUT D18
0x4844AD04 0 1500 CFG_XREF_CLK1_OUT E17
0x4844A3C8 0 800 CFG_MCASP1_AXR0_OUT G12
0x4844A41C 0 1400 CFG_MCASP1_AXR1_OUT F12
0x4844A470 0 2000 CFG_MCASP1_AXR8_OUT B12
0x4844A47C 0 800 CFG_MCASP1_AXR9_OUT A11
0x4844A3D4 0 2300 CFG_MCASP1_AXR10_OUT B13
0x4844A3E0 0 600 CFG_MCASP1_AXR11_OUT A12
0x4844A3F8 0 1500 CFG_MCASP1_AXR13_OUT A13
0x4844ABA8 0 0 CFG_VOUT1_D0_OUT F11
0x4844AC2C 0 0 CFG_VOUT1_D1_OUT G10
/* PinMux automatically generated generic format file dump. */
/* register_address(hex) register_value(hex) ball_name(string)
register_name(string) mux_mode0_name(string) muxed_mode_name(string) */
0x4A003570 0x1000A D1 CTRL_CORE_PAD_VIN2A_D2 vin2a_d2
eCAP1_in_PWM1_out
0x4A003780 0x5000A AC4 CTRL_CORE_PAD_MMC3_CMD mmc3_cmd
eCAP2_in_PWM2_out
0x4A0037A0 0x1000A AB5 CTRL_CORE_PAD_MMC3_DAT7 mmc3_dat7
eCAP3_in_PWM3_out
0x4A003794 0x5000E AC8 CTRL_CORE_PAD_MMC3_DAT4 mmc3_dat4 gpio1_22
0x4A003798 0x5000E AD6 CTRL_CORE_PAD_MMC3_DAT5 mmc3_dat5 gpio1_23
0x4A00379C 0x5000E AB8 CTRL_CORE_PAD_MMC3_DAT6 mmc3_dat6 gpio1_24
0x4A00378C 0x5000E AC9 CTRL_CORE_PAD_MMC3_DAT2 mmc3_dat2 gpio7_1
0x4A003790 0x5000E AC3 CTRL_CORE_PAD_MMC3_DAT3 mmc3_dat3 gpio7_2
0x4A003510 0x5000E AH4 CTRL_CORE_PAD_VIN1A_D7 vin1a_d7 gpio3_11
0x4A003624 0x5000E A7 CTRL_CORE_PAD_VOUT1_D18 vout1_d18 gpio8_18
0x4A00358C 0x5000E E6 CTRL_CORE_PAD_VIN2A_D9 vin2a_d9 gpio4_10
0x4A0036F0 0xD000E F14 CTRL_CORE_PAD_MCASP1_AXR15 mcasp1_axr15
gpio6_6
0x4A00377C 0x5000E AD4 CTRL_CORE_PAD_MMC3_CLK mmc3_clk gpio6_29
0x4A003784 0x5000E AC7 CTRL_CORE_PAD_MMC3_DAT0 mmc3_dat0 gpio6_31
0x4A003440 0x50007 R6 CTRL_CORE_PAD_GPMC_A0 gpmc_a0 i2c4_scl
0x4A003444 0x50007 T9 CTRL_CORE_PAD_GPMC_A1 gpmc_a1 i2c4_sda
0x4A0035EC 0x1000A E9 CTRL_CORE_PAD_VOUT1_D4 vout1_d4
pr1_ecap0_ecap_capin_apwm_o
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A003590 0x1010D D3 CTRL_CORE_PAD_VIN2A_D10 vin2a_d10
pr1_pru1_gpo7
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A003598 0x1010D D5 CTRL_CORE_PAD_VIN2A_D12 vin2a_d12
pr1_pru1_gpo9
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A00359C 0x1010D C2 CTRL_CORE_PAD_VIN2A_D13 vin2a_d13
pr1_pru1_gpo10
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035AC 0x1010D D6 CTRL_CORE_PAD_VIN2A_D17 vin2a_d17
pr1_pru1_gpo14
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035B0 0x1010D C5 CTRL_CORE_PAD_VIN2A_D18 vin2a_d18
pr1_pru1_gpo15
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035B8 0x1010D B3 CTRL_CORE_PAD_VIN2A_D20 vin2a_d20
pr1_pru1_gpo17
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035BC 0x1010D B4 CTRL_CORE_PAD_VIN2A_D21 vin2a_d21
pr1_pru1_gpo18
/* PR1_PRU1_DIR_IN_MANUAL */
0x4A0035A0 0x5010C C3 CTRL_CORE_PAD_VIN2A_D14 vin2a_d14
pr1_pru1_gpi11
0x4A0035E4 0x5000A F10 CTRL_CORE_PAD_VOUT1_D2 vout1_d2
pr1_uart0_rxd
0x4A0035E8 0x1000A G11 CTRL_CORE_PAD_VOUT1_D3 vout1_d3
pr1_uart0_txd
0x4A003618 0x1000A C7 CTRL_CORE_PAD_VOUT1_D15 vout1_d15
pr2_ecap0_ecap_capin_apwm_o
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A003694 0x1010D D18 CTRL_CORE_PAD_XREF_CLK0 xref_clk0
pr2_pru1_gpo5
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A003698 0x1010D E17 CTRL_CORE_PAD_XREF_CLK1 xref_clk1
pr2_pru1_gpo6
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036B4 0x9010D G12 CTRL_CORE_PAD_MCASP1_AXR0 mcasp1_axr0
pr2_pru1_gpo8
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036B8 0x9010D F12 CTRL_CORE_PAD_MCASP1_AXR1 mcasp1_axr1
pr2_pru1_gpo9
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036D4 0x9010D B12 CTRL_CORE_PAD_MCASP1_AXR8 mcasp1_axr8
pr2_pru1_gpo10
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036D8 0x9010D A11 CTRL_CORE_PAD_MCASP1_AXR9 mcasp1_axr9
pr2_pru1_gpo11
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036DC 0x9010D B13 CTRL_CORE_PAD_MCASP1_AXR10 mcasp1_axr10
pr2_pru1_gpo12
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036E0 0x9010D A12 CTRL_CORE_PAD_MCASP1_AXR11 mcasp1_axr11
pr2_pru1_gpo13
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036E8 0x9010D A13 CTRL_CORE_PAD_MCASP1_AXR13 mcasp1_axr13
pr2_pru1_gpo15
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0035DC 0x1010D F11 CTRL_CORE_PAD_VOUT1_D0 vout1_d0
pr2_pru1_gpo18
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0035E0 0x1010D G10 CTRL_CORE_PAD_VOUT1_D1 vout1_d1
pr2_pru1_gpo19
0x4A003610 0x5000A C6 CTRL_CORE_PAD_VOUT1_D13 vout1_d13
pr2_uart0_rxd
0x4A003614 0x1000A C8 CTRL_CORE_PAD_VOUT1_D14 vout1_d14
pr2_uart0_txd
0x4A0036EC 0xD000A G14 CTRL_CORE_PAD_MCASP1_AXR14 mcasp1_axr14
timer11
0x4A0037C0 0x50001 A26 CTRL_CORE_PAD_SPI2_SCLK spi2_sclk
uart3_rxd
0x4A0037C4 0x90001 B22 CTRL_CORE_PAD_SPI2_D1 spi2_d1 uart3_txd
Design Signal Pad Name,IO Power Group,PUPD State During HHV,PUPD State After HHV,IO Power Supply Name,IO Power Setting,Required Voltage Level,Ball Name,Mode Interface Name,Mode Signal Name,Mode Type,User Checked PU,User Checked PD,User Checked RX,User Requirement Name
vin2a_d2,vin2,PD,PD,vddshv1,,,D1,eCAP1,eCAP1_in_PWM1_out,,FALSE,FALSE,FALSE,PWM1
mmc3_cmd,wifi,PU,PU,vddshv7,,,AC4,eCAP2,eCAP2_in_PWM2_out,,FALSE,FALSE,TRUE,PWM2
mmc3_dat7,wifi,PU,PU,vddshv7,,,AB5,eCAP3,eCAP3_in_PWM3_out,,FALSE,FALSE,FALSE,PWM3
mmc3_dat4,wifi,PU,PU,vddshv7,,,AC8,GPIO1,gpio1_22,,FALSE,FALSE,TRUE,GPIO1
mmc3_dat5,wifi,PU,PU,vddshv7,,,AD6,GPIO1,gpio1_23,,FALSE,FALSE,TRUE,GPIO1
mmc3_dat6,wifi,PU,PU,vddshv7,,,AB8,GPIO1,gpio1_24,,FALSE,FALSE,TRUE,GPIO1
mmc3_dat2,wifi,PU,PU,vddshv7,,,AC9,GPIO7,gpio7_1,,FALSE,FALSE,TRUE,GPIO7
mmc3_dat3,wifi,PU,PU,vddshv7,,,AC3,GPIO7,gpio7_2,,FALSE,FALSE,TRUE,GPIO7
vin1a_d7,vin1,PD,PD,vddshv6,,,AH4,GPIO3,gpio3_11,,FALSE,FALSE,TRUE,GPIO3
vout1_d18,vout1,PD,PD,vddshv2,,,A7,GPIO8,gpio8_18,,FALSE,FALSE,TRUE,GPIO8
vin2a_d9,vin2,PD,PD,vddshv1,,,E6,GPIO4,gpio4_10,,FALSE,FALSE,TRUE,GPIO4
mcasp1_axr15,general,PD,PD,vddshv3,,,F14,GPIO6,gpio6_6,,FALSE,FALSE,TRUE,GPIO6
mmc3_clk,wifi,PU,PU,vddshv7,,,AD4,GPIO6,gpio6_29,,FALSE,FALSE,TRUE,GPIO6
mmc3_dat0,wifi,PU,PU,vddshv7,,,AC7,GPIO6,gpio6_31,,FALSE,FALSE,TRUE,GPIO6
gpmc_a0,gpmc,PD,PD,vddshv10,,,R6,I2C4,i2c4_scl,,FALSE,FALSE,TRUE,TestBus
gpmc_a1,gpmc,PD,PD,vddshv10,,,T9,I2C4,i2c4_sda,,FALSE,FALSE,TRUE,TestBus
vout1_d4,vout1,PD,PD,vddshv2,,,E9,PRUSS1_eCAP,pr1_ecap0_ecap_capin_apwm_o,,FALSE,FALSE,FALSE,PRU1_PWM
vin2a_d10,vin2,PD,PD,vddshv1,,,D3,PRUSS1_PRU1,pr1_pru1_gpo7,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d12,vin2,PD,PD,vddshv1,,,D5,PRUSS1_PRU1,pr1_pru1_gpo9,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d13,vin2,PD,PD,vddshv1,,,C2,PRUSS1_PRU1,pr1_pru1_gpo10,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d17,vin2,PD,PD,vddshv1,,,D6,PRUSS1_PRU1,pr1_pru1_gpo14,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d18,vin2,PD,PD,vddshv1,,,C5,PRUSS1_PRU1,pr1_pru1_gpo15,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d20,vin2,PD,PD,vddshv1,,,B3,PRUSS1_PRU1,pr1_pru1_gpo17,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d21,vin2,PD,PD,vddshv1,,,B4,PRUSS1_PRU1,pr1_pru1_gpo18,,FALSE,FALSE,FALSE,PRU1_GPIO
vin2a_d14,vin2,PD,PD,vddshv1,,,C3,PRUSS1_PRU1,pr1_pru1_gpi11,,FALSE,FALSE,TRUE,PRU1_GPIO
vout1_d2,vout1,PD,PD,vddshv2,,,F10,PRUSS1_UART,pr1_uart0_rxd,,FALSE,FALSE,TRUE,PRU1_Debug_UART
vout1_d3,vout1,PD,PD,vddshv2,,,G11,PRUSS1_UART,pr1_uart0_txd,,FALSE,FALSE,FALSE,PRU1_Debug_UART
vout1_d15,vout1,PD,PD,vddshv2,,,C7,PRUSS2_eCAP,pr2_ecap0_ecap_capin_apwm_o,,FALSE,FALSE,FALSE,MyPRUSS2_eCAP1
xref_clk0,general,PD,PD,vddshv3,,,D18,PRUSS2_PRU1,pr2_pru1_gpo5,,FALSE,FALSE,FALSE,PRU2_GPIO
xref_clk1,general,PD,PD,vddshv3,,,E17,PRUSS2_PRU1,pr2_pru1_gpo6,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr0,general,PD,PD,vddshv3,,,G12,PRUSS2_PRU1,pr2_pru1_gpo8,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr1,general,PD,PD,vddshv3,,,F12,PRUSS2_PRU1,pr2_pru1_gpo9,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr8,general,PD,PD,vddshv3,,,B12,PRUSS2_PRU1,pr2_pru1_gpo10,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr9,general,PD,PD,vddshv3,,,A11,PRUSS2_PRU1,pr2_pru1_gpo11,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr10,general,PD,PD,vddshv3,,,B13,PRUSS2_PRU1,pr2_pru1_gpo12,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr11,general,PD,PD,vddshv3,,,A12,PRUSS2_PRU1,pr2_pru1_gpo13,,FALSE,FALSE,FALSE,PRU2_GPIO
mcasp1_axr13,general,PD,PD,vddshv3,,,A13,PRUSS2_PRU1,pr2_pru1_gpo15,,FALSE,FALSE,FALSE,PRU2_GPIO
vout1_d0,vout1,PD,PD,vddshv2,,,F11,PRUSS2_PRU1,pr2_pru1_gpo18,,FALSE,FALSE,FALSE,PRU2_GPIO
vout1_d1,vout1,PD,PD,vddshv2,,,G10,PRUSS2_PRU1,pr2_pru1_gpo19,,FALSE,FALSE,FALSE,PRU2_GPIO
vout1_d13,vout1,PD,PD,vddshv2,,,C6,PRUSS2_UART,pr2_uart0_rxd,,FALSE,FALSE,TRUE,PRU2_Debug_UART
vout1_d14,vout1,PD,PD,vddshv2,,,C8,PRUSS2_UART,pr2_uart0_txd,,FALSE,FALSE,FALSE,PRU2_Debug_UART
mcasp1_axr14,general,PD,PD,vddshv3,,,G14,TIMER11,timer11,,FALSE,FALSE,TRUE,MAIN_TIMER
spi2_sclk,general,PD,PD,vddshv3,,,A26,UART3,uart3_rxd,,FALSE,FALSE,TRUE,MAIN_DEBUG_UART
spi2_d1,general,PD,PD,vddshv3,,,B22,UART3,uart3_txd,,FALSE,FALSE,FALSE,MAIN_DEBUG_UART
/**
* Note: This file was auto-generated by TI PinMux on 4/25/2020 at 2:10:14 PM.
*
* \file devicetree.txt
*
* \brief This file should only be used as a reference! This file contains
* register configuration information for the AM57xx Control Module. Two
* formats are provided in this file. The device tree (.dts) format WHICH
* MAY CHANGE BETWEEN LINUX KERNEL VERSIONS and a generic format. For
* summarization and description of the pad register bits refer to the
* "Control Module" chapter of the device Data Manual. This file should only
* be used as a reference. Some pins and/or peripherals, depending on your
* use case, may need additional configuration. Only MMC modes are exported
* here. All other pad configuration must be done by u-boot.
*
**/
/* * DEVICE TREE FORMAT PADCONF * */
&dra7_pmx_core {
};
/* * DEVICE TREE FORMAT IODELAY * */
&dra7_iodelay_core {
// for linux kernel 4.4 / processor sdk 3.x
};
/* * GENERIC FORMAT PADCONF * */
/* * GENERIC FORMAT IODELAY * */
