Are there any plans to implement this in the future? If not, is the device
tree the only way to set up the pin muxing?

On Tue, Sep 8, 2020, 5:23 PM Robert Nelson <[email protected]> wrote:

>
>
> On Tue, Sep 8, 2020, 5:19 PM Diane Miller <[email protected]>
> wrote:
>
>> Where can I find the format of the cape EEPROM pin usage section for the
>> BeagleBone AI? I need to know the ordering of the pins as well as the
>> format of each pin's 16-bit field.
>>
>> From what I could figure out on my own the BBB pins are in GPIO order,
>> with the non-muxed AINx pins at the end of the table. Can anyone confirm
>> that this same ordering applies to the BBAI? How are the a/b pins handled
>> (such as 9.19a/b)?
>>
>> It seems that the BBAI pin bitfield's format must differ from the BBB
>> since the AM572x has a 4-bit muxmode field, whereas the AM335x has only 3
>> bits. Has the BBAI's EEPROM format been posted anywhere?
>>
>
>
> This feature of the spec was never utilized.
>
>
>
> Regards
>
>>
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