Could you tell something more about how could a spilledReg be a physical register? This is not very clear for me. If a virtual register is to be spilled, then it will always be a virtual register, and will be unspilled when it is used. When it may become a physical register?
On Fri, Aug 9, 2013 at 1:23 PM, Ruiling Song <[email protected]> wrote: > We can only spill virtual registers, should skip physical register. > This fix random failure of compiler_box_blur when do spilling. > > Signed-off-by: Ruiling Song <[email protected]> > --- > backend/src/backend/gen_insn_selection.cpp | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/backend/src/backend/gen_insn_selection.cpp > b/backend/src/backend/gen_insn_selection.cpp > index 3610051..5cafa98 100644 > --- a/backend/src/backend/gen_insn_selection.cpp > +++ b/backend/src/backend/gen_insn_selection.cpp > @@ -628,12 +628,15 @@ namespace gbe > > for (auto &block : blockList) > for (auto &insn : block.insnList) { > + // spill / unspill insn should be skipped when do spilling > + if(insn.opcode == SEL_OP_SPILL_REG || insn.opcode == > SEL_OP_UNSPILL_REG) continue; > + > const uint32_t srcNum = insn.srcNum, dstNum = insn.dstNum; > > for (uint32_t srcID = 0; srcID < srcNum; ++srcID) { > const GenRegister selReg = insn.src(srcID); > const ir::Register reg = selReg.reg(); > - if(selReg.file == GEN_GENERAL_REGISTER_FILE && reg == > spilledReg) { > + if(reg == spilledReg && selReg.file == > GEN_GENERAL_REGISTER_FILE && selReg.physical == 0) { > GBE_ASSERT(srcID < 5); > SelectionInstruction *unspill = > this->create(SEL_OP_UNSPILL_REG, 1, 0); > unspill->state = GenInstructionState(simdWidth); > @@ -652,7 +655,7 @@ namespace gbe > for (uint32_t dstID = 0; dstID < dstNum; ++dstID) { > const GenRegister selReg = insn.dst(dstID); > const ir::Register reg = selReg.reg(); > - if(selReg.file == GEN_GENERAL_REGISTER_FILE && reg == > spilledReg) { > + if(reg == spilledReg && selReg.file == > GEN_GENERAL_REGISTER_FILE && selReg.physical == 0) { > GBE_ASSERT(dstID < 5); > SelectionInstruction *spill = this->create(SEL_OP_SPILL_REG, > 0, 1); > spill->state = GenInstructionState(simdWidth); > -- > 1.7.9.5 > > _______________________________________________ > Beignet mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/beignet >
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