lgtm -----Original Message----- From: Beignet [mailto:[email protected]] On Behalf Of Zhigang Gong Sent: Thursday, April 17, 2014 5:42 PM To: [email protected] Cc: Gong, Zhigang Subject: [Beignet] [PATCH] GBE: fix a Q64 spilling bug in non-simd8 mode.
For simd16 mode, the payload need to have 2 GRFs not the hard coded 1 GRF. This patch fixes the corresponding regression on piglit. Signed-off-by: Zhigang Gong <[email protected]> --- backend/src/backend/gen_insn_selection.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index f7f438e..72a8549 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -725,7 +725,7 @@ namespace gbe && selReg.physical == 0) { ir::RegisterFamily family = getRegisterFamily(reg); if(family == ir::FAMILY_QWORD && poolOffset == 1) { - poolOffset += 1; // qword register fill could not share the scratch read message payload register + poolOffset += simdWidth / 8; // qword register fill could + not share the scratch read message payload register } struct RegSlot regSlot(reg, srcID, poolOffset, it->second.isTmpReg, @@ -786,7 +786,7 @@ namespace gbe && selReg.physical == 0) { ir::RegisterFamily family = getRegisterFamily(reg); if(family == ir::FAMILY_QWORD && poolOffset == 1) { - poolOffset += 1; // qword register spill could not share the scratch write message payload register + poolOffset += simdWidth / 8; // qword register spill + could not share the scratch write message payload register } struct RegSlot regSlot(reg, dstID, poolOffset, it->second.isTmpReg, -- 1.8.3.2 _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
