I met the same issue on baytrail, and the solution is to just try not to
reduce the URB too much when enable SLM.
The patchset LGTM, and wait for testing report.
On Fri, May 30, 2014 at 12:37:34AM +0800, Yang Rong wrote:
> It seems L3 control register is per context in IVB, but not per context
> in HSW, so need restore the L3 control register, otherwise, it may cause
> screen flick.
> this patch may hurt some performance.
>
> Signed-off-by: Yang Rong <rong.r.y...@intel.com>
> ---
> src/intel/intel_gpgpu.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
> index 2cde179..b4cfa57 100644
> --- a/src/intel/intel_gpgpu.c
> +++ b/src/intel/intel_gpgpu.c
> @@ -124,6 +124,9 @@ intel_gpgpu_set_L3_t *intel_gpgpu_set_L3 = NULL;
> typedef uint32_t (intel_gpgpu_get_scratch_index_t)(uint32_t size);
> intel_gpgpu_get_scratch_index_t *intel_gpgpu_get_scratch_index = NULL;
>
> +typedef void (intel_gpgpu_post_action_t)(intel_gpgpu_t *gpgpu, int32_t
> flush_mode);
> +intel_gpgpu_post_action_t *intel_gpgpu_post_action = NULL;
> +
> static void
> intel_gpgpu_sync(void *buf)
> {
> @@ -480,6 +483,24 @@ intel_gpgpu_batch_start(intel_gpgpu_t *gpgpu)
> }
>
> static void
> +intel_gpgpu_post_action_gen7(intel_gpgpu_t *gpgpu, int32_t flush_mode)
> +{
> + if(flush_mode)
> + intel_gpgpu_pipe_control(gpgpu);
> +}
> +
> +static void
> +intel_gpgpu_post_action_gen75(intel_gpgpu_t *gpgpu, int32_t flush_mode)
> +{
> + /* flush force for set L3 */
> + intel_gpgpu_pipe_control(gpgpu);
> +
> + /* Restore L3 control to disable SLM mode,
> + otherwise, may affect 3D pipeline */
> + intel_gpgpu_set_L3(gpgpu, 0);
> +}
> +
> +static void
> intel_gpgpu_batch_end(intel_gpgpu_t *gpgpu, int32_t flush_mode)
> {
> /* Insert PIPE_CONTROL for time stamp of end*/
> @@ -501,7 +522,7 @@ intel_gpgpu_batch_end(intel_gpgpu_t *gpgpu, int32_t
> flush_mode)
> ADVANCE_BATCH(gpgpu->batch);
> }
>
> - if(flush_mode) intel_gpgpu_pipe_control(gpgpu);
> + intel_gpgpu_post_action(gpgpu, flush_mode);
> intel_batchbuffer_end_atomic(gpgpu->batch);
> }
>
> @@ -1216,6 +1237,7 @@ intel_set_gpgpu_callbacks(int device_id)
> intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen75;
> cl_gpgpu_get_cache_ctrl = (cl_gpgpu_get_cache_ctrl_cb
> *)intel_gpgpu_get_cache_ctrl_gen75;
> intel_gpgpu_get_scratch_index = intel_gpgpu_get_scratch_index_gen75;
> + intel_gpgpu_post_action = intel_gpgpu_post_action_gen75;
> }
> else if (IS_IVYBRIDGE(device_id)) {
> cl_gpgpu_bind_image = (cl_gpgpu_bind_image_cb *)
> intel_gpgpu_bind_image_gen7;
> @@ -1225,6 +1247,7 @@ intel_set_gpgpu_callbacks(int device_id)
> intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen7;
> cl_gpgpu_get_cache_ctrl = (cl_gpgpu_get_cache_ctrl_cb
> *)intel_gpgpu_get_cache_ctrl_gen7;
> intel_gpgpu_get_scratch_index = intel_gpgpu_get_scratch_index_gen7;
> + intel_gpgpu_post_action = intel_gpgpu_post_action_gen7;
> }
> else
> assert(0);
> --
> 1.8.3.2
>
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