This version LGTM, just pushed, thanks.
On Thu, Oct 16, 2014 at 04:51:12PM +0800, Yang Rong wrote: > In GenEncoder, unpack is not good, so move the upsample int/short from > GenEncoder to instruction selection. > Still handle upsample long in GenContext. > > Signed-off-by: Yang Rong <[email protected]> > --- > backend/src/backend/gen_context.cpp | 2 -- > backend/src/backend/gen_encoder.cpp | 18 ------------------ > backend/src/backend/gen_encoder.hpp | 2 -- > backend/src/backend/gen_insn_selection.cpp | 22 ++++++++++++++++++---- > backend/src/backend/gen_insn_selection.hxx | 2 -- > 5 files changed, 18 insertions(+), 28 deletions(-) > > diff --git a/backend/src/backend/gen_context.cpp > b/backend/src/backend/gen_context.cpp > index ead455f..c05d4e7 100644 > --- a/backend/src/backend/gen_context.cpp > +++ b/backend/src/backend/gen_context.cpp > @@ -442,8 +442,6 @@ namespace gbe > case SEL_OP_ADD: p->ADD(dst, src0, src1); break; > case SEL_OP_MUL: p->MUL(dst, src0, src1); break; > case SEL_OP_MACH: p->MACH(dst, src0, src1); break; > - case SEL_OP_UPSAMPLE_SHORT: p->UPSAMPLE_SHORT(dst, src0, src1); break; > - case SEL_OP_UPSAMPLE_INT: p->UPSAMPLE_INT(dst, src0, src1); break; > case SEL_OP_UPSAMPLE_LONG: > { > GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL), > diff --git a/backend/src/backend/gen_encoder.cpp > b/backend/src/backend/gen_encoder.cpp > index 847ab7b..589617f 100644 > --- a/backend/src/backend/gen_encoder.cpp > +++ b/backend/src/backend/gen_encoder.cpp > @@ -612,24 +612,6 @@ namespace gbe > pop(); > } > > - void GenEncoder::UPSAMPLE_SHORT(GenRegister dest, GenRegister src0, > GenRegister src1) { > - dest = GenRegister::retype(GenRegister::unpacked_uw(dest.nr, > dest.subnr), GEN_TYPE_B); > - src0 = GenRegister::retype(GenRegister::unpacked_uw(src0.nr, > src0.subnr), GEN_TYPE_B); > - src1 = GenRegister::retype(GenRegister::unpacked_uw(src1.nr, > src1.subnr), GEN_TYPE_B); > - MOV(dest, src1); > - dest.subnr ++; > - MOV(dest, src0); > - } > - > - void GenEncoder::UPSAMPLE_INT(GenRegister dest, GenRegister src0, > GenRegister src1) { > - dest = GenRegister::unpacked_uw(dest.nr, dest.subnr); > - src0 = GenRegister::unpacked_uw(src0.nr, src0.subnr); > - src1 = GenRegister::unpacked_uw(src1.nr, src1.subnr); > - MOV(dest, src1); > - dest.subnr += 2; > - MOV(dest, src0); > - } > - > void GenEncoder::LOAD_INT64_IMM(GenRegister dest, int64_t value) { > GenRegister u0 = GenRegister::immd((int)value), u1 = > GenRegister::immd(value >> 32); > MOV(dest.bottom_half(), u0); > diff --git a/backend/src/backend/gen_encoder.hpp > b/backend/src/backend/gen_encoder.hpp > index 3df7a57..9170d70 100644 > --- a/backend/src/backend/gen_encoder.hpp > +++ b/backend/src/backend/gen_encoder.hpp > @@ -101,8 +101,6 @@ namespace gbe > ALU1(FBL) > ALU1(CBIT) > ALU2(SUBB) > - ALU2(UPSAMPLE_SHORT) > - ALU2(UPSAMPLE_INT) > ALU1(RNDZ) > ALU1(RNDE) > ALU1(RNDD) > diff --git a/backend/src/backend/gen_insn_selection.cpp > b/backend/src/backend/gen_insn_selection.cpp > index 2b7bf47..5ca363a 100644 > --- a/backend/src/backend/gen_insn_selection.cpp > +++ b/backend/src/backend/gen_insn_selection.cpp > @@ -498,8 +498,6 @@ namespace gbe > ALU1(CBIT) > ALU2WithTemp(HADD) > ALU2WithTemp(RHADD) > - ALU2(UPSAMPLE_SHORT) > - ALU2(UPSAMPLE_INT) > ALU2(UPSAMPLE_LONG) > ALU1WithTemp(CONVI_TO_I64) > ALU1WithTemp(CONVF_TO_I64) > @@ -2291,11 +2289,27 @@ namespace gbe > break; > } > case OP_UPSAMPLE_SHORT: > - sel.UPSAMPLE_SHORT(dst, src0, src1); > + { > + dst = GenRegister::retype(sel.unpacked_uw(dst.reg()), GEN_TYPE_B); > + src0 = GenRegister::retype(sel.unpacked_uw(src0.reg()), > GEN_TYPE_B); > + src1 = GenRegister::retype(sel.unpacked_uw(src1.reg()), > GEN_TYPE_B); > + sel.MOV(dst, src1); > + dst.subphysical = 1; > + dst = dst.offset(dst, 0, typeSize(GEN_TYPE_B)); > + sel.MOV(dst, src0); > break; > + } > case OP_UPSAMPLE_INT: > - sel.UPSAMPLE_INT(dst, src0, src1); > + { > + dst = sel.unpacked_uw(dst.reg()); > + src0 = sel.unpacked_uw(src0.reg()); > + src1 = sel.unpacked_uw(src1.reg()); > + sel.MOV(dst, src1); > + dst.subphysical = 1; > + dst = dst.offset(dst, 0, typeSize(GEN_TYPE_W)); > + sel.MOV(dst, src0); > break; > + } > case OP_UPSAMPLE_LONG: > sel.UPSAMPLE_LONG(dst, src0, src1); > break; > diff --git a/backend/src/backend/gen_insn_selection.hxx > b/backend/src/backend/gen_insn_selection.hxx > index d80dc58..da8086e 100644 > --- a/backend/src/backend/gen_insn_selection.hxx > +++ b/backend/src/backend/gen_insn_selection.hxx > @@ -73,8 +73,6 @@ DECL_SELECTION_IR(HADD, BinaryWithTempInstruction) > DECL_SELECTION_IR(RHADD, BinaryWithTempInstruction) > DECL_SELECTION_IR(I64HADD, I64HADDInstruction) > DECL_SELECTION_IR(I64RHADD, I64RHADDInstruction) > -DECL_SELECTION_IR(UPSAMPLE_SHORT, BinaryInstruction) > -DECL_SELECTION_IR(UPSAMPLE_INT, BinaryInstruction) > DECL_SELECTION_IR(UPSAMPLE_LONG, BinaryInstruction) > DECL_SELECTION_IR(CONVI_TO_I64, UnaryWithTempInstruction) > DECL_SELECTION_IR(CONVI64_TO_I, UnaryInstruction) > -- > 1.9.1 > > _______________________________________________ > Beignet mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
