Is there anybody can verify this patch on BDW? Thanks.
On Mon, Oct 20, 2014 at 03:46:17PM +0800, Yang Rong wrote: > Global constant buffer size is not align to 4 byte, will cause assert in BDW > when set bti. > Per spec, the low two bits of surface state's width must be 11 if > SURFACE_BUFFER's format is RAW. > Align the global constant buffer size to 4. > > Signed-off-by: Yang Rong <[email protected]> > --- > src/cl_command_queue_gen7.c | 6 +++++- > src/intel/intel_gpgpu.c | 10 +++++++++- > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/src/cl_command_queue_gen7.c b/src/cl_command_queue_gen7.c > index d847806..225bb34 100644 > --- a/src/cl_command_queue_gen7.c > +++ b/src/cl_command_queue_gen7.c > @@ -109,7 +109,11 @@ cl_upload_constant_buffer(cl_command_queue queue, > cl_kernel ker) > gbe_program prog = ker->program->opaque; > const int32_t arg_n = interp_kernel_get_arg_num(ker->opaque); > size_t global_const_size = interp_program_get_global_constant_size(prog); > - aligned_size = raw_size = global_const_size; > + raw_size = global_const_size; > + // Surface state need 4 byte alignment, and Constant argument's buffer size > + // have align to 4 byte when alloc, so align global constant size to 4 can > + // ensure the finally aligned_size align to 4. > + aligned_size = ALIGN(raw_size, 4); > /* Reserve 8 bytes to get rid of 0 address */ > if(global_const_size == 0) aligned_size = 8; > > diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c > index 167d8d9..69c7771 100644 > --- a/src/intel/intel_gpgpu.c > +++ b/src/intel/intel_gpgpu.c > @@ -848,6 +848,9 @@ intel_gpgpu_setup_bti_gen7(intel_gpgpu_t *gpgpu, > drm_intel_bo *buf, uint32_t int > ss0->ss0.surface_type = I965_SURFACE_BUFFER; > ss0->ss0.surface_format = format; > ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */ > + // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple > of 4 byte. > + if(format == I965_SURFACEFORMAT_RAW) > + assert((ss0->ss2.width & 0x03) == 3); > ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */ > ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */ > ss0->ss5.cache_control = cl_gpgpu_get_cache_ctrl(); > @@ -881,6 +884,9 @@ intel_gpgpu_setup_bti_gen75(intel_gpgpu_t *gpgpu, > drm_intel_bo *buf, uint32_t in > ss0->ss7.shader_a = I965_SURCHAN_SELECT_ALPHA; > } > ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */ > + // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple > of 4 byte. > + if(format == I965_SURFACEFORMAT_RAW) > + assert((ss0->ss2.width & 0x03) == 3); > ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */ > ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */ > ss0->ss5.cache_control = cl_gpgpu_get_cache_ctrl(); > @@ -914,7 +920,9 @@ intel_gpgpu_setup_bti_gen8(intel_gpgpu_t *gpgpu, > drm_intel_bo *buf, uint32_t int > ss0->ss7.shader_channel_select_alpha = I965_SURCHAN_SELECT_ALPHA; > } > ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */ > - assert(ss0->ss2.width & 0x03); > + // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple > of 4 byte. > + if(format == I965_SURFACEFORMAT_RAW) > + assert((ss0->ss2.width & 0x03) == 3); > ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */ > ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */ > ss0->ss1.mem_obj_ctrl_state = cl_gpgpu_get_cache_ctrl(); > -- > 1.9.1 > > _______________________________________________ > Beignet mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
