[Beignet] [PATCH] correct the src output of alu3 when OCL_OUTPUT_ASM=1

[Guo Yejun]

Signed-off-by: Guo Yejun <yejun....@intel.com>
---
 backend/src/backend/gen/gen_mesa_disasm.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/backend/src/backend/gen/gen_mesa_disasm.c 
b/backend/src/backend/gen/gen_mesa_disasm.c
index f8d89e0..705f5e2 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -831,7 +831,10 @@ static int src0_3src(FILE *file, const void* inst)
     return 0;
   if (GEN_BITS_FIELD(inst, bits2.da3src.src0_subreg_nr))
     format(file, ".%d", GEN_BITS_FIELD(inst, bits2.da3src.src0_subreg_nr));
-  string(file, "<4,1,1>");
+  if (GEN_BITS_FIELD(inst, bits2.da3src.src0_rep_ctrl))
+    string(file, "<0,1,0>");
+  else
+    string(file, "<8,8,1>");
   err |= control(file, "src da16 reg type", reg_encoding,
                  GEN_TYPE_F, NULL);
   /*
@@ -876,7 +879,10 @@ static int src1_3src(FILE *file, const void* inst)
     return 0;
   if (src1_subreg_nr)
     format(file, ".%d", src1_subreg_nr);
-  string(file, "<4,1,1>");
+  if (GEN_BITS_FIELD(inst, bits2.da3src.src1_rep_ctrl))
+    string(file, "<0,1,0>");
+  else
+    string(file, "<8,8,1>");
   err |= control(file, "src da16 reg type", reg_encoding,
                  GEN_TYPE_F, NULL);
   /*
@@ -918,7 +924,10 @@ static int src2_3src(FILE *file, const void* inst)
     return 0;
   if (GEN_BITS_FIELD(inst, bits3.da3src.src2_subreg_nr))
     format(file, ".%d", GEN_BITS_FIELD(inst, bits3.da3src.src2_subreg_nr));
-  string(file, "<4,1,1>");
+  if (GEN_BITS_FIELD(inst, bits3.da3src.src2_rep_ctrl))
+    string(file, "<0,1,0>");
+  else
+    string(file, "<8,8,1>");
   err |= control(file, "src da16 reg type", reg_encoding,
                  GEN_TYPE_F, NULL);
   /*
-- 
1.9.1

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