From: Junyan He <junyan...@linux.intel.com>
F16TO32 and F32TO16 have been used by vload functions.
So for consistency of code path, we will use them to do half
and float conversions.
Signed-off-by: Junyan He <junyan...@linux.intel.com>
---
backend/src/llvm/llvm_gen_backend.cpp | 24 ++++++++++++++++++++++++
backend/src/llvm/llvm_gen_ocl_function.hxx | 7 +++++++
2 files changed, 31 insertions(+)
diff --git a/backend/src/llvm/llvm_gen_backend.cpp
b/backend/src/llvm/llvm_gen_backend.cpp
index 912bccb..37c9e7b 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -3037,6 +3037,12 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
ctx.SEL(dstType, dst, src, oneReg, zeroReg);
}
+ /* For half <---> float conversion, we use F16TO32 or F32TO16, make
the code path same. */
+ else if (srcType == ir::TYPE_HALF && dstType == ir::TYPE_FLOAT) {
+ ctx.F16TO32(ir::TYPE_FLOAT, ir::TYPE_U16, getRegister(&I),
getRegister(I.getOperand(0)));
+ } else if (srcType == ir::TYPE_FLOAT && dstType == ir::TYPE_HALF) {
+ ctx.F32TO16(ir::TYPE_U16, ir::TYPE_FLOAT, getRegister(&I),
getRegister(I.getOperand(0)));
+ }
// Use a convert for the other cases
else {
const ir::Register dst = this->getRegister(&I);
@@ -3398,6 +3404,12 @@ namespace gbe
case GEN_OCL_SAT_CONV_F32_TO_I32:
case GEN_OCL_SAT_CONV_I32_TO_U32:
case GEN_OCL_SAT_CONV_F32_TO_U32:
+ case GEN_OCL_SAT_CONV_F16_TO_I8:
+ case GEN_OCL_SAT_CONV_F16_TO_U8:
+ case GEN_OCL_SAT_CONV_F16_TO_I16:
+ case GEN_OCL_SAT_CONV_F16_TO_U16:
+ case GEN_OCL_SAT_CONV_F16_TO_I32:
+ case GEN_OCL_SAT_CONV_F16_TO_U32:
case GEN_OCL_CONV_F16_TO_F32:
case GEN_OCL_CONV_F32_TO_F16:
case GEN_OCL_SIMD_ANY:
@@ -4068,6 +4080,18 @@ namespace gbe
DEF(ir::TYPE_U32, ir::TYPE_S32);
case GEN_OCL_SAT_CONV_F32_TO_U32:
DEF(ir::TYPE_U32, ir::TYPE_FLOAT);
+ case GEN_OCL_SAT_CONV_F16_TO_I8:
+ DEF(ir::TYPE_S8, ir::TYPE_HALF);
+ case GEN_OCL_SAT_CONV_F16_TO_U8:
+ DEF(ir::TYPE_U8, ir::TYPE_HALF);
+ case GEN_OCL_SAT_CONV_F16_TO_I16:
+ DEF(ir::TYPE_S16, ir::TYPE_HALF);
+ case GEN_OCL_SAT_CONV_F16_TO_U16:
+ DEF(ir::TYPE_U16, ir::TYPE_HALF);
+ case GEN_OCL_SAT_CONV_F16_TO_I32:
+ DEF(ir::TYPE_S32, ir::TYPE_HALF);
+ case GEN_OCL_SAT_CONV_F16_TO_U32:
+ DEF(ir::TYPE_U32, ir::TYPE_HALF);
case GEN_OCL_CONV_F16_TO_F32:
ctx.F16TO32(ir::TYPE_FLOAT, ir::TYPE_U16, getRegister(&I),
getRegister(I.getOperand(0)));
break;
diff --git a/backend/src/llvm/llvm_gen_ocl_function.hxx
b/backend/src/llvm/llvm_gen_ocl_function.hxx
index 671e785..cabb225 100644
--- a/backend/src/llvm/llvm_gen_ocl_function.hxx
+++ b/backend/src/llvm/llvm_gen_ocl_function.hxx
@@ -151,6 +151,13 @@ DECL_LLVM_GEN_FUNCTION(SAT_CONV_F32_TO_U32,
_Z16convert_uint_satf)
DECL_LLVM_GEN_FUNCTION(CONV_F16_TO_F32, __gen_ocl_f16to32)
DECL_LLVM_GEN_FUNCTION(CONV_F32_TO_F16, __gen_ocl_f32to16)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_I8, _Z16convert_char_satDh)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_U8, _Z17convert_uchar_satDh)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_I16, _Z17convert_short_satDh)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_U16, _Z18convert_ushort_satDh)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_I32, _Z15convert_int_satDh)
+DECL_LLVM_GEN_FUNCTION(SAT_CONV_F16_TO_U32, _Z16convert_uint_satDh)
+
// SIMD level function for internal usage
DECL_LLVM_GEN_FUNCTION(SIMD_ANY, sub_group_any)
DECL_LLVM_GEN_FUNCTION(SIMD_ALL, sub_group_all)
--
1.9.1
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