LGTM, thanks.
> -----Original Message----- > From: Beignet [mailto:[email protected]] On Behalf Of > Guo Yejun > Sent: Friday, October 23, 2015 3:10 > To: [email protected] > Cc: Guo, Yejun > Subject: [Beignet] [PATCH] add comments to explain 32bit is enough to > represent w+hstrid+vstride > > Signed-off-by: Guo Yejun <[email protected]> > --- > backend/src/backend/gen_insn_selection_optimize.cpp | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp > b/backend/src/backend/gen_insn_selection_optimize.cpp > index fffc8b0..8df531c 100644 > --- a/backend/src/backend/gen_insn_selection_optimize.cpp > +++ b/backend/src/backend/gen_insn_selection_optimize.cpp > @@ -27,6 +27,10 @@ namespace gbe > uint32_t offsetInByte = base; > for (uint32_t j = 0; j < width; ++j) { > uint32_t offsetInType = offsetInByte / elementSize; > + //it is possible that offsetInType > 32, it doesn't matter even > elements > is 32 bit. > + //the reseason is that if one instruction span several registers, > + //the other registers' visit pattern is same as first register if > the vstride is > normal(width * hstride) > + assert(vstride == width * hstride); > elements |= (1 << offsetInType); > offsetInByte += hstride * elementSize; > } > -- > 1.9.1 > > _______________________________________________ > Beignet mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/beignet
