From: Junyan He <junyan...@linux.intel.com>
Because just platform after BDW will support double,
the special instruction for double MOV is not needed
anymore.
Signed-off-by: Junyan He <junyan...@linux.intel.com>
---
backend/src/backend/gen75_encoder.cpp | 36 -------------------------
backend/src/backend/gen75_encoder.hpp | 1 -
backend/src/backend/gen8_encoder.cpp | 36 -------------------------
backend/src/backend/gen8_encoder.hpp | 1 -
backend/src/backend/gen_context.cpp | 3 ---
backend/src/backend/gen_encoder.cpp | 43 ------------------------------
backend/src/backend/gen_encoder.hpp | 2 --
backend/src/backend/gen_insn_selection.cpp | 23 +---------------
backend/src/backend/gen_insn_selection.hxx | 1 -
9 files changed, 1 insertion(+), 145 deletions(-)
diff --git a/backend/src/backend/gen75_encoder.cpp
b/backend/src/backend/gen75_encoder.cpp
index 135be02..5d1a964 100644
--- a/backend/src/backend/gen75_encoder.cpp
+++ b/backend/src/backend/gen75_encoder.cpp
@@ -251,42 +251,6 @@ namespace gbe
pop();
}
- void Gen75Encoder::MOV_DF(GenRegister dest, GenRegister src0, GenRegister
tmp) {
- GBE_ASSERT((src0.type == GEN_TYPE_F && dest.isdf()) || (src0.isdf() &&
dest.type == GEN_TYPE_F));
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_F);
- int w = curr.execWidth;
- GenRegister r0;
- r0 = GenRegister::h2(r);
- push();
- curr.execWidth = 4;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, src0);
- MOV(GenRegister::suboffset(r0, 4), GenRegister::suboffset(src0, 4));
- curr.noMask = 0;
- curr.quarterControl = 0;
- curr.nibControl = 0;
- MOV(dest, r0);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 4), GenRegister::suboffset(r0, 4));
- pop();
- if (w == 16) {
- push();
- curr.execWidth = 4;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, GenRegister::suboffset(src0, 8));
- MOV(GenRegister::suboffset(r0, 4), GenRegister::suboffset(src0, 12));
- curr.noMask = 0;
- curr.quarterControl = 1;
- curr.nibControl = 0;
- MOV(GenRegister::suboffset(dest, 8), r0);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 12), GenRegister::suboffset(r0, 4));
- pop();
- }
- }
-
void Gen75Encoder::JMPI(GenRegister src, bool longjmp) {
alu2(this, GEN_OPCODE_JMPI, GenRegister::ip(), GenRegister::ip(), src);
}
diff --git a/backend/src/backend/gen75_encoder.hpp
b/backend/src/backend/gen75_encoder.hpp
index e494f29..f5044c0 100644
--- a/backend/src/backend/gen75_encoder.hpp
+++ b/backend/src/backend/gen75_encoder.hpp
@@ -42,7 +42,6 @@ namespace gbe
virtual void JMPI(GenRegister src, bool longjmp = false);
/*! Patch JMPI/BRC/BRD (located at index insnID) with the given jump
distance */
virtual void patchJMPI(uint32_t insnID, int32_t jip, int32_t uip);
- virtual void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp =
GenRegister::null());
virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void ATOMIC(GenRegister dst, uint32_t function, GenRegister src,
GenRegister bti, uint32_t srcNum);
virtual void UNTYPED_READ(GenRegister dst, GenRegister src, GenRegister
bti, uint32_t elemNum);
diff --git a/backend/src/backend/gen8_encoder.cpp
b/backend/src/backend/gen8_encoder.cpp
index 55fc3fb..98c3917 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -260,42 +260,6 @@ namespace gbe
MOV(dest, value);
}
- void Gen8Encoder::MOV_DF(GenRegister dest, GenRegister src0, GenRegister
tmp) {
- GBE_ASSERT((src0.type == GEN_TYPE_F && dest.isdf()) || (src0.isdf() &&
dest.type == GEN_TYPE_F));
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_F);
- int w = curr.execWidth;
- GenRegister r0;
- r0 = GenRegister::h2(r);
- push();
- curr.execWidth = 4;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, src0);
- MOV(GenRegister::suboffset(r0, 4), GenRegister::suboffset(src0, 4));
- curr.noMask = 0;
- curr.quarterControl = 0;
- curr.nibControl = 0;
- MOV(dest, r0);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 4), GenRegister::suboffset(r0, 4));
- pop();
- if (w == 16) {
- push();
- curr.execWidth = 4;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, GenRegister::suboffset(src0, 8));
- MOV(GenRegister::suboffset(r0, 4), GenRegister::suboffset(src0, 12));
- curr.noMask = 0;
- curr.quarterControl = 1;
- curr.nibControl = 0;
- MOV(GenRegister::suboffset(dest, 8), r0);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 12), GenRegister::suboffset(r0, 4));
- pop();
- }
- }
-
void Gen8Encoder::JMPI(GenRegister src, bool longjmp) {
alu2(this, GEN_OPCODE_JMPI, GenRegister::ip(), GenRegister::ip(), src);
}
diff --git a/backend/src/backend/gen8_encoder.hpp
b/backend/src/backend/gen8_encoder.hpp
index 4cd3664..2aa074f 100644
--- a/backend/src/backend/gen8_encoder.hpp
+++ b/backend/src/backend/gen8_encoder.hpp
@@ -42,7 +42,6 @@ namespace gbe
virtual void patchJMPI(uint32_t insnID, int32_t jip, int32_t uip);
virtual void F16TO32(GenRegister dest, GenRegister src0);
virtual void F32TO16(GenRegister dest, GenRegister src0);
- virtual void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp =
GenRegister::null());
virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void LOAD_INT64_IMM(GenRegister dest, GenRegister value);
virtual void ATOMIC(GenRegister dst, uint32_t function, GenRegister src,
GenRegister bti, uint32_t srcNum);
diff --git a/backend/src/backend/gen_context.cpp
b/backend/src/backend/gen_context.cpp
index 4e2ebfb..cad7802 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -332,9 +332,6 @@ namespace gbe
case SEL_OP_LOAD_DF_IMM:
p->LOAD_DF_IMM(dst, tmp, src.value.df);
break;
- case SEL_OP_MOV_DF:
- p->MOV_DF(dst, src, tmp);
- break;
case SEL_OP_CONVI_TO_I64: {
GenRegister middle = src;
if(src.type == GEN_TYPE_B || src.type == GEN_TYPE_W) {
diff --git a/backend/src/backend/gen_encoder.cpp
b/backend/src/backend/gen_encoder.cpp
index 2cc51cc..a6daa0d 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -763,49 +763,6 @@ namespace gbe
MOV(dest.top_half(this->simdWidth), u1);
}
- void GenEncoder::MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp)
{
- GBE_ASSERT((src0.type == GEN_TYPE_F && dest.isdf()) || (src0.isdf() &&
dest.type == GEN_TYPE_F));
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_F);
- int w = curr.execWidth;
- GenRegister r0;
- int factor = 1;
- if (dest.type == GEN_TYPE_F) {
- r0 = r;
- r = GenRegister::h2(r);
- factor = 2;
- } else {
- r0 = GenRegister::h2(r);
- }
- push();
- curr.execWidth = 8;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, src0);
- MOV(GenRegister::suboffset(r0, 4 * factor), GenRegister::suboffset(src0,
4));
- curr.noMask = 0;
- curr.quarterControl = 0;
- curr.nibControl = 0;
- MOV(dest, r);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 4), GenRegister::suboffset(r, 8 /
factor));
- pop();
- if (w == 16) {
- push();
- curr.execWidth = 8;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- MOV(r0, GenRegister::suboffset(src0, 8));
- MOV(GenRegister::suboffset(r0, 4 * factor), GenRegister::suboffset(src0,
12));
- curr.noMask = 0;
- curr.quarterControl = 1;
- curr.nibControl = 0;
- MOV(GenRegister::suboffset(dest, 8), r);
- curr.nibControl = 1;
- MOV(GenRegister::suboffset(dest, 12), GenRegister::suboffset(r, 8 /
factor));
- pop();
- }
- }
-
void GenEncoder::F16TO32(GenRegister dest, GenRegister src0) {
alu1(this, GEN_OPCODE_F16TO32, dest, src0);
}
diff --git a/backend/src/backend/gen_encoder.hpp
b/backend/src/backend/gen_encoder.hpp
index f2bb5ab..3e9866c 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -125,7 +125,6 @@ namespace gbe
ALU2(LINE)
ALU2(PLN)
ALU3(MAD)
- //ALU2(MOV_DF);
ALU2(BRC)
ALU1(BRD)
#undef ALU1
@@ -135,7 +134,6 @@ namespace gbe
virtual void F16TO32(GenRegister dest, GenRegister src0);
virtual void F32TO16(GenRegister dest, GenRegister src0);
- virtual void MOV_DF(GenRegister dest, GenRegister src0, GenRegister tmp =
GenRegister::null());
virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void LOAD_INT64_IMM(GenRegister dest, GenRegister value);
/*! Barrier message (to synchronize threads of a workgroup) */
diff --git a/backend/src/backend/gen_insn_selection.cpp
b/backend/src/backend/gen_insn_selection.cpp
index 2452aea..58b7cb4 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -516,7 +516,6 @@ namespace gbe
INLINE void OP(Reg dst, Reg src0, Reg src1, GenRegister tmp[6]) {
I64Shift(SEL_OP_##OP, dst, src0, src1, tmp); }
ALU1(MOV)
ALU1(READ_ARF)
- ALU1WithTemp(MOV_DF)
ALU1WithTemp(LOAD_DF_IMM)
ALU1(LOAD_INT64_IMM)
ALU1(RNDZ)
@@ -2452,10 +2451,7 @@ namespace gbe
}
break;
case ir::OP_MOV:
- if (dst.isdf()) {
- ir::Register r = sel.reg(ir::RegisterFamily::FAMILY_QWORD);
- sel.MOV_DF(dst, src, sel.selReg(r, ir::TYPE_U64));
- } else {
+ {
sel.push();
auto dag = sel.regDAG[insn.getDst(0)];
if (sel.getRegisterFamily(insn.getDst(0)) == ir::FAMILY_BOOL &&
@@ -4635,28 +4631,11 @@ namespace gbe
INLINE void convertBetweenFloatDouble(Selection::Opaque &sel, const
ir::ConvertInstruction &insn, bool &markChildren) const
{
using namespace ir;
- const Type dstType = insn.getDstType();
- const Type srcType = insn.getSrcType();
- const GenRegister dst = sel.selReg(insn.getDst(0), dstType);
- const GenRegister src = sel.selReg(insn.getSrc(0), srcType);
-
-
- //TODO:
- ir::Register r = sel.reg(ir::RegisterFamily::FAMILY_QWORD);
- sel.MOV_DF(dst, src, sel.selReg(r, TYPE_U64));
}
INLINE void convertBetweenHalfDouble(Selection::Opaque &sel, const
ir::ConvertInstruction &insn, bool &markChildren) const
{
using namespace ir;
- const Type dstType = insn.getDstType();
- const Type srcType = insn.getSrcType();
- const GenRegister dst = sel.selReg(insn.getDst(0), dstType);
- const GenRegister src = sel.selReg(insn.getSrc(0), srcType);
-
- //TODO:
- ir::Register r = sel.reg(ir::RegisterFamily::FAMILY_QWORD);
- sel.MOV_DF(dst, src, sel.selReg(r, TYPE_U64));
}
INLINE void convertHalfToSmallInts(Selection::Opaque &sel, const
ir::ConvertInstruction &insn, bool &markChildren) const
diff --git a/backend/src/backend/gen_insn_selection.hxx
b/backend/src/backend/gen_insn_selection.hxx
index 479398b..1f248be 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -1,7 +1,6 @@
DECL_SELECTION_IR(LABEL, LabelInstruction)
DECL_SELECTION_IR(MOV, UnaryInstruction)
DECL_SELECTION_IR(BSWAP, UnaryWithTempInstruction)
-DECL_SELECTION_IR(MOV_DF, UnaryWithTempInstruction)
DECL_SELECTION_IR(LOAD_DF_IMM, UnaryWithTempInstruction)
DECL_SELECTION_IR(LOAD_INT64_IMM, UnaryInstruction)
DECL_SELECTION_IR(NOT, UnaryInstruction)
--
1.9.1
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