> -----Original Message-----
> From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
> junyan...@inbox.com
> Sent: Tuesday, December 1, 2015 16:11
> To: beignet@lists.freedesktop.org
> Subject: [Beignet] [PATCH 07/13] Backend: Add WORKGROUP_OP instruction
> selection.
>
> From: Junyan He <junyan...@linux.intel.com>
>
> Signed-off-by: Junyan He <junyan...@linux.intel.com>
> ---
> backend/src/backend/gen_context.cpp | 3 ++
> backend/src/backend/gen_context.hpp | 1 +
> .../src/backend/gen_insn_gen7_schedule_info.hxx | 1 +
> backend/src/backend/gen_insn_selection.cpp | 34
> ++++++++++++++++++++
> backend/src/backend/gen_insn_selection.hpp | 1 +
> backend/src/backend/gen_insn_selection.hxx | 1 +
> 6 files changed, 41 insertions(+)
>
> diff --git a/backend/src/backend/gen_context.cpp
> b/backend/src/backend/gen_context.cpp
> index 43fa7fa..5c819b7 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -2844,6 +2844,9 @@ namespace gbe
> } p->pop();
> }
>
> + void GenContext::emitWorkGroupOpInstruction(const
> + SelectionInstruction &insn) { }
> +
> void GenContext::setA0Content(uint16_t new_a0[16], uint16_t max_offset,
> int sz) {
> if (sz == 0)
> sz = 8;
> diff --git a/backend/src/backend/gen_context.hpp
> b/backend/src/backend/gen_context.hpp
> index da9bbbe..22ec0ea 100644
> --- a/backend/src/backend/gen_context.hpp
> +++ b/backend/src/backend/gen_context.hpp
> @@ -179,6 +179,7 @@ namespace gbe
> virtual void emitF64DIVInstruction(const SelectionInstruction &insn);
> void emitCalcTimestampInstruction(const SelectionInstruction &insn);
> void emitStoreProfilingInstruction(const SelectionInstruction &insn);
> + void emitWorkGroupOpInstruction(const SelectionInstruction &insn);
> void scratchWrite(const GenRegister header, uint32_t offset, uint32_t
> reg_num, uint32_t reg_type, uint32_t channel_mode);
> void scratchRead(const GenRegister dst, const GenRegister header,
> uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t
> channel_mode);
> unsigned beforeMessage(const SelectionInstruction &insn, GenRegister
> bti, GenRegister flagTemp, GenRegister btiTmp, unsigned desc); diff --git
> a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> index 739cc04..8ef422f 100644
> --- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> +++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> @@ -47,3 +47,4 @@ DECL_GEN7_SCHEDULE(I64SATSUB, 20, 40, 20)
> DECL_GEN7_SCHEDULE(F64DIV, 20, 40, 20)
> DECL_GEN7_SCHEDULE(CalcTimestamp, 80, 1, 1)
> DECL_GEN7_SCHEDULE(StoreProfiling, 80, 1, 1)
> +DECL_GEN7_SCHEDULE(WorkGroupOp, 80, 1,
> 1)
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index 5b08958..536d347 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -680,6 +680,9 @@ namespace gbe
> void I64REM(Reg dst, Reg src0, Reg src1, GenRegister *tmp, int tmp_int);
> /*! double division */
> void F64DIV(Reg dst, Reg src0, Reg src1, GenRegister* tmp, int tmpNum);
> + /*! Work Group Operations */
> + void WORKGROUP_OP(uint32_t wg_op, Reg dst, GenRegister src,
> GenRegister nextThreadID,
> + GenRegister threadID, GenRegister threadn,
> + GenRegister tmp);
> /* common functions for both binary instruction and sel_cmp and
> compare instruction.
> It will handle the IMM or normal register assignment, and will try to
> avoid
> LOADI
> as much as possible. */
> @@ -1897,6 +1900,20 @@ namespace gbe
> }
> }
>
> + void Selection::Opaque::WORKGROUP_OP(uint32_t wg_op, Reg dst,
> GenRegister src, GenRegister nextThreadID,
> + GenRegister threadID, GenRegister threadn, GenRegister
> tmp) {
> + SelectionInstruction *insn = this->appendInsn(SEL_OP_WORKGROUP_OP,
> 3, 4);
> + insn->extra.workgroupOp = wg_op;
> + insn->dst(0) = dst;
> + insn->dst(1) = nextThreadID;
Use nextThreadID as src and dst meanwhile?
> + insn->dst(2) = tmp;
> +
> + insn->src(0) = src;
> + insn->src(1) = nextThreadID;
> + insn->src(2) = threadID;
> + insn->src(3) = threadn;
> + }
> +
> // Boiler plate to initialize the selection library at c++ pre-main
> static SelectionLibrary *selLib = NULL;
> static void destroySelectionLibrary(void) { GBE_DELETE(selLib); } @@ -
> 6166,9 +6183,26 @@ namespace gbe
>
> /* Third, get the next thread ID which we will Forward MSG to. */
> GenRegister nextThreadID = getNextThreadID(sel, slmAddr);
> + GenRegister threadID = sel.selReg(ocl::threadid, ir::TYPE_U32);
> + GenRegister threadNum = sel.selReg(ocl::threadn, ir::TYPE_U32);
> + GenRegister tmp =
> + GenRegister::retype(sel.selReg(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD);
> +
> + const Type type = insn.getType();
> + const GenRegister dst = sel.selReg(insn.getDst(0), type);
> + const uint32_t srcNum = insn.getSrcNum();
> + GBE_ASSERT(srcNum == 3);
> + GBE_ASSERT(insn.getSrc(0) == ir::ocl::threadn);
> + GBE_ASSERT(insn.getSrc(1) == ir::ocl::threadid);
> + GenRegister src = sel.selReg(insn.getSrc(2), type);
> + sel.push(); {
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> + sel.WORKGROUP_OP(workGroupOp, dst, src, nextThreadID, threadID,
> threadNum, tmp);
> + } sel.pop();
> } else {
> GBE_ASSERT(0);
> }
> +
> return true;
> }
> DECL_CTOR(WorkGroupInstruction, 1, 1); diff --git
> a/backend/src/backend/gen_insn_selection.hpp
> b/backend/src/backend/gen_insn_selection.hpp
> index 0070ac2..65f9da0 100644
> --- a/backend/src/backend/gen_insn_selection.hpp
> +++ b/backend/src/backend/gen_insn_selection.hpp
> @@ -147,6 +147,7 @@ namespace gbe
> uint32_t profilingType:16;
> uint32_t profilingBTI:16;
> };
> + uint32_t workgroupOp;
> } extra;
> /*! Gen opcode */
> uint8_t opcode;
> diff --git a/backend/src/backend/gen_insn_selection.hxx
> b/backend/src/backend/gen_insn_selection.hxx
> index bc09522..0f824eb 100644
> --- a/backend/src/backend/gen_insn_selection.hxx
> +++ b/backend/src/backend/gen_insn_selection.hxx
> @@ -92,3 +92,4 @@ DECL_SELECTION_IR(WHILE, UnaryInstruction)
> DECL_SELECTION_IR(F64DIV, F64DIVInstruction)
> DECL_SELECTION_IR(CALC_TIMESTAMP, CalcTimestampInstruction)
> DECL_SELECTION_IR(STORE_PROFILING, StoreProfilingInstruction)
> +DECL_SELECTION_IR(WORKGROUP_OP, WorkGroupOpInstruction)
> --
> 1.7.9.5
>
>
>
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