[Beignet] [PATCH 3/6] Backend: Fix simd shuffle base address

[Xiuli Pan]

From: Pan Xiuli <xiuli....@intel.com>

In genregister subnr is in byte, this will not infulence register that
is 32 align which subnr is 0, but will get wrong base address for simd8
HF or W type register if they have nozero subnr.

Signed-off-by: Pan Xiuli <xiuli....@intel.com>
---
 backend/src/backend/gen8_context.cpp | 2 +-
 backend/src/backend/gen_context.cpp  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/backend/src/backend/gen8_context.cpp 
b/backend/src/backend/gen8_context.cpp
index 5809835..a520e61 100644
--- a/backend/src/backend/gen8_context.cpp
+++ b/backend/src/backend/gen8_context.cpp
@@ -328,7 +328,7 @@ namespace gbe
     assert(insn.opcode == SEL_OP_SIMD_SHUFFLE);
     assert (src1.file != GEN_IMMEDIATE_VALUE);
 
-    uint32_t base = src0.nr * 32 + src0.subnr * 4;
+    uint32_t base = src0.nr * 32 + src0.subnr;
     GenRegister baseReg = GenRegister::immuw(base);
     const GenRegister a0 = GenRegister::addr8(0);
     p->ADD(a0, GenRegister::unpacked_uw(src1.nr, src1.subnr / 
typeSize(GEN_TYPE_UW)), baseReg);
diff --git a/backend/src/backend/gen_context.cpp 
b/backend/src/backend/gen_context.cpp
index 33f1026..6afa470 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -702,7 +702,7 @@ namespace gbe
     assert(insn.opcode == SEL_OP_SIMD_SHUFFLE);
     assert (src1.file != GEN_IMMEDIATE_VALUE);
 
-    uint32_t base = src0.nr * 32 + src0.subnr * 4;
+    uint32_t base = src0.nr * 32 + src0.subnr;
     GenRegister baseReg = GenRegister::immuw(base);
     const GenRegister a0 = GenRegister::addr8(0);
     uint32_t simd = p->curr.execWidth;
-- 
2.7.4

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