this [PATCH 1/2] looks good, it helps the logical 1:1 mapping between virtual register and physical register.
-----Original Message----- From: Beignet [mailto:[email protected]] On Behalf Of Xiuli Pan Sent: Thursday, November 24, 2016 5:53 PM To: [email protected] Cc: Pan, Xiuli Subject: [Beignet] [PATCH 1/2] Backend: Add RegisterFamily for ir From: Pan Xiuli <[email protected]> We may need some bigger family like OWORD or HWORD and 32 word will be a reg. This can be used for tmp and header registers. Signed-off-by: Pan Xiuli <[email protected]> --- backend/src/backend/gen_reg_allocation.cpp | 8 ++++++-- backend/src/ir/register.cpp | 3 +++ backend/src/ir/register.hpp | 8 ++++++-- backend/src/ir/type.hpp | 4 ++-- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp index 495d830..522d8fd 100644 --- a/backend/src/backend/gen_reg_allocation.cpp +++ b/backend/src/backend/gen_reg_allocation.cpp @@ -92,8 +92,12 @@ namespace gbe const bool isScalar = ctx.sel->isScalarReg(reg); const RegisterData regData = ctx.sel->getRegisterData(reg); const RegisterFamily family = regData.family; - const uint32_t typeSize = isScalar ? familyScalarSize[family] : familyVectorSize[family]; - regSize = isScalar ? typeSize : ctx.getSimdWidth() * typeSize; + if (family == ir::FAMILY_REG) + regSize = 32; + else { + const uint32_t typeSize = isScalar ? familyScalarSize[family] : familyVectorSize[family]; + regSize = isScalar ? typeSize : ctx.getSimdWidth() * typeSize; + } if (regFamily != NULL) *regFamily = family; } diff --git a/backend/src/ir/register.cpp b/backend/src/ir/register.cpp index 8200c31..1e78722 100644 --- a/backend/src/ir/register.cpp +++ b/backend/src/ir/register.cpp @@ -35,6 +35,9 @@ namespace ir { case FAMILY_WORD: return out << "word"; case FAMILY_DWORD: return out << "dword"; case FAMILY_QWORD: return out << "qword"; + case FAMILY_OWORD: return out << "oword"; + case FAMILY_HWORD: return out << "hword"; + case FAMILY_REG: return out << "reg"; }; return out; } diff --git a/backend/src/ir/register.hpp b/backend/src/ir/register.hpp index 11ab756..09af24e 100644 --- a/backend/src/ir/register.hpp +++ b/backend/src/ir/register.hpp @@ -45,11 +45,14 @@ namespace ir { FAMILY_BYTE = 1, FAMILY_WORD = 2, FAMILY_DWORD = 3, - FAMILY_QWORD = 4 + FAMILY_QWORD = 4, + FAMILY_OWORD = 5, + FAMILY_HWORD = 6, + FAMILY_REG = 7 }; INLINE char getFamilyName(RegisterFamily family) { - static char registerFamilyName[] = {'b', 'B', 'W', 'D', 'Q'}; + static char registerFamilyName[] = {'b', 'B', 'W', 'D', 'Q', 'O', 'H', 'R'}; return registerFamilyName[family]; } @@ -59,6 +62,7 @@ namespace ir { case FAMILY_WORD: return 2; case FAMILY_DWORD: return 4; case FAMILY_QWORD: return 8; + case FAMILY_REG: return 32; default: NOT_SUPPORTED; }; return 0; diff --git a/backend/src/ir/type.hpp b/backend/src/ir/type.hpp index d528859..3ac758f 100644 --- a/backend/src/ir/type.hpp +++ b/backend/src/ir/type.hpp @@ -86,8 +86,8 @@ namespace ir { case FAMILY_WORD: return TYPE_U16; case FAMILY_DWORD: return TYPE_U32; case FAMILY_QWORD: return TYPE_U64; - }; - return TYPE_U32; + default: return TYPE_U32; + } } } /* namespace ir */ -- 2.7.4 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
