hi, please ignore all my un-pushed patches.
I got a new idea after discussed with Xiuli, I'll add a function parameter 'useSends' for the encoder, so we can switch instructions sends and send inside the encoder function even if all the message payloads are continuous. thanks yejun -----Original Message----- From: Guo, Yejun Sent: Wednesday, December 07, 2016 7:10 PM To: [email protected] Cc: Guo, Yejun Subject: [PATCH 3/3] enable sends for typed write Signed-off-by: Guo, Yejun <[email protected]> --- backend/src/backend/gen9_encoder.cpp | 20 +++++++++++++++++++ backend/src/backend/gen9_encoder.hpp | 1 + backend/src/backend/gen_context.cpp | 5 ++++- backend/src/backend/gen_insn_selection.cpp | 31 ++++++++++++++++++++++++------ backend/src/backend/gen_insn_selection.hpp | 1 + 5 files changed, 51 insertions(+), 7 deletions(-) diff --git a/backend/src/backend/gen9_encoder.cpp b/backend/src/backend/gen9_encoder.cpp index b5be852..35fbcb9 100644 --- a/backend/src/backend/gen9_encoder.cpp +++ b/backend/src/backend/gen9_encoder.cpp @@ -144,6 +144,26 @@ namespace gbe } } + void Gen9Encoder::TYPED_WRITE(GenRegister header, GenRegister data, + bool header_present, unsigned char bti) { + if (header.reg() == data.reg()) + Gen8Encoder::TYPED_WRITE(header, data, header_present, bti); + else { + GenNativeInstruction *insn = this->next(GEN_OPCODE_SENDS); + Gen9NativeInstruction *gen9_insn = &insn->gen9_insn; + assert(header_present); + + this->setHeader(insn); + insn->header.destreg_or_condmod = GEN_SFID_DATAPORT1_DATA; + + setSendsOperands(gen9_insn, GenRegister::null(), header, data); + gen9_insn->bits2.sends.src1_length = 4; //src0_length: 5(header+u+v+w+lod), src1_length: 4(data) + + gen9_insn->bits2.sends.sel_reg32_desc = 0; + setTypedWriteMessage(insn, bti, GEN_TYPED_WRITE, 5, header_present); + } + } + unsigned Gen9Encoder::setByteScatterSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemSize) { uint32_t msg_length = 0; diff --git a/backend/src/backend/gen9_encoder.hpp b/backend/src/backend/gen9_encoder.hpp index 1c40b92..20f269f 100644 --- a/backend/src/backend/gen9_encoder.hpp +++ b/backend/src/backend/gen9_encoder.hpp @@ -49,6 +49,7 @@ namespace gbe bool isUniform); void setSendsOperands(Gen9NativeInstruction *gen9_insn, GenRegister dst, GenRegister src0, GenRegister src1); virtual void UNTYPED_WRITE(GenRegister addr, GenRegister data, GenRegister bti, uint32_t elemNum); + virtual void TYPED_WRITE(GenRegister header, GenRegister data, bool + header_present, unsigned char bti); virtual unsigned setUntypedWriteSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemNum); virtual void BYTE_SCATTER(GenRegister addr, GenRegister data, GenRegister bti, uint32_t elemSize); virtual unsigned setByteScatterSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemSize); diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 302a65b..090470f 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -2461,8 +2461,11 @@ namespace gbe void GenContext::emitTypedWriteInstruction(const SelectionInstruction &insn) { const GenRegister header = GenRegister::retype(ra->genReg(insn.src(0)), GEN_TYPE_UD); + GenRegister data = ra->genReg(insn.src(5)); + if (!insn.extra.typedWriteSplitSend) + data = header; const uint32_t bti = insn.getbti(); - p->TYPED_WRITE(header, header, true, bti); + p->TYPED_WRITE(header, data, true, bti); } static void calcGID(GenRegister& reg, GenRegister& tmp, int flag, int subFlag, int dim, GenContext *gc) diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 94c5e9e..44d7fbc 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2759,7 +2759,6 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp uint32_t elemID = 0; uint32_t i; SelectionInstruction *insn = this->appendInsn(SEL_OP_TYPED_WRITE, 0, msgNum); - SelectionVector *msgVector = this->appendVector();; for( i = 0; i < msgNum; ++i, ++elemID) insn->src(elemID) = msgs[i]; @@ -2767,11 +2766,31 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp insn->setbti(bti); insn->extra.msglen = msgNum; insn->extra.is3DWrite = is3D; - // Sends require contiguous allocation - msgVector->regNum = msgNum; - msgVector->isSrc = 1; - msgVector->offsetID = 0; - msgVector->reg = &insn->src(0); + + if (hasSends()) { + assert(msgNum == 9); + insn->extra.typedWriteSplitSend = 1; + //header + coords + SelectionVector *msgVector = this->appendVector(); + msgVector->regNum = 5; + msgVector->isSrc = 1; + msgVector->offsetID = 0; + msgVector->reg = &insn->src(0); + + //data + msgVector = this->appendVector(); + msgVector->regNum = 4; + msgVector->isSrc = 1; + msgVector->offsetID = 5; + msgVector->reg = &insn->src(5); + } else { + // Send require contiguous allocation + SelectionVector *msgVector = this->appendVector(); + msgVector->regNum = msgNum; + msgVector->isSrc = 1; + msgVector->offsetID = 0; + msgVector->reg = &insn->src(0); + } } Selection::~Selection(void) { GBE_DELETE(this->opaque); } diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp index 7ce2b94..4b22ed2 100644 --- a/backend/src/backend/gen_insn_selection.hpp +++ b/backend/src/backend/gen_insn_selection.hpp @@ -124,6 +124,7 @@ namespace gbe uint16_t bti:8; uint16_t msglen:5; uint16_t is3DWrite:1; + uint16_t typedWriteSplitSend:1; }; struct { uint16_t rdbti:8; -- 1.9.1 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
