From: Pan Xiuli <[email protected]> When refine the block read/write we miss something about the A64.
Signed-off-by: Pan Xiuli <[email protected]> --- backend/src/backend/gen8_encoder.cpp | 3 +-- backend/src/backend/gen_insn_selection.cpp | 6 ++++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp index b274a51..a33fbac 100644 --- a/backend/src/backend/gen8_encoder.cpp +++ b/backend/src/backend/gen8_encoder.cpp @@ -829,14 +829,13 @@ namespace gbe { const GenMessageTarget sfid = GEN_SFID_DATAPORT1_DATA; p->setMessageDescriptor(insn, sfid, msg_length, response_length); - assert(size == 0 || size == 1 || size == 2 || size == 4 || size == 8); Gen8NativeInstruction *gen8_insn = &insn->gen8_insn; gen8_insn->bits3.gen8_block_rw_a64.msg_type = msg_type; gen8_insn->bits3.gen8_block_rw_a64.bti = bti; // For OWord Block read, we use unaligned read gen8_insn->bits3.gen8_block_rw_a64.msg_sub_type = msg_type == GEN8_P1_BLOCK_READ_A64 ? 1 : 0; - gen8_insn->bits3.gen8_block_rw_a64.block_size = size <= 2 ? size : (size == 4 ? 3 : 4); + gen8_insn->bits3.gen8_block_rw_a64.block_size = size; gen8_insn->bits3.gen8_block_rw_a64.header_present = 1; } diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 1adeb8c..2093f4f 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2358,7 +2358,8 @@ namespace gbe insn->setbti(bti); insn->extra.elem = ow_size; // number of OWord_size - if (hasSends()) { + // For A64 write, we did not add sends support yet. + if (hasSends() && bti != 255) { insn->extra.splitSend = 1; SelectionVector *vector = this->appendVector(); vector->regNum = 1; @@ -5301,6 +5302,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp const uint32_t genType = type == TYPE_U32 ? GEN_TYPE_UD : GEN_TYPE_UW; const RegisterFamily family = getFamily(type); bool isA64 = SI == 255; + uint32_t offset_size = isA64 ? 128 : 8; const GenRegister header = GenRegister::ud8grf(sel.reg(FAMILY_REG)); vector<GenRegister> valuesVec; @@ -5364,7 +5366,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp { // Update the address in header sel.curr.execWidth = 1; - sel.ADD(headeraddr, headeraddr, GenRegister::immud(8)); + sel.ADD(headeraddr, headeraddr, GenRegister::immud(offset_size)); } sel.pop(); } -- 2.7.4 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
