GEN's div instruction need several cycles, use the shl instruction when divisor is pow of 2 constant.
Signed-off-by: Yang Rong <[email protected]> --- backend/src/llvm/llvm_gen_backend.cpp | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 5c5266c..3fefa92 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -3295,7 +3295,18 @@ namespace gbe case Instruction::URem: ctx.REM(getUnsignedType(ctx, I.getType()), dst, src0, src1); break; case Instruction::SRem: case Instruction::FRem: ctx.REM(type, dst, src0, src1); break; - case Instruction::UDiv: ctx.DIV(getUnsignedType(ctx, I.getType()), dst, src0, src1); break; + case Instruction::UDiv: + { + //Only check divisor for DIV + ConstantInt *c = dyn_cast<ConstantInt>(I.getOperand(1)); + if (c != NULL && isPowerOf<2>(c->getZExtValue())) { + c = ConstantInt::get(c->getType(), logi2(c->getZExtValue())); + ctx.SHR(getUnsignedType(ctx, I.getType()), dst, src0, this->getRegister(c)); + } else { + ctx.DIV(getUnsignedType(ctx, I.getType()), dst, src0, src1); + } + break; + } case Instruction::SDiv: case Instruction::FDiv: ctx.DIV(type, dst, src0, src1); break; case Instruction::And: ctx.AND(type, dst, src0, src1); break; -- 2.7.4 _______________________________________________ Beignet mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/beignet
