From: Pan Xiuli <xiuli....@intel.com>
In selection stage physical register usage may cause some random assert
in reg alloction as there is no virtual register for these physical
register.
Signed-off-by: Pan Xiuli <xiuli....@intel.com>
---
backend/src/backend/gen_insn_selection.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp
b/backend/src/backend/gen_insn_selection.cpp
index ea538d0..4aa6033 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -4775,7 +4775,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling
BVAR in program.cpp
sel.curr.execWidth = 8;
sel.curr.predicate = GEN_PREDICATE_NONE;
sel.curr.noMask = 1;
- sel.MOV(header, GenRegister::ud8grf(0, 0));
+ sel.MOV(header, GenRegister::immud(0));
// Update the header with the current address
sel.curr.execWidth = 1;
@@ -5283,7 +5283,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling
BVAR in program.cpp
sel.curr.execWidth = 8;
sel.curr.predicate = GEN_PREDICATE_NONE;
sel.curr.noMask = 1;
- sel.MOV(header, GenRegister::ud8grf(0, 0));
+ sel.MOV(header, GenRegister::immud(0));
// Update the header with the current address
sel.curr.execWidth = 1;
@@ -7873,7 +7873,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling
BVAR in program.cpp
sel.curr.execWidth = 8;
sel.curr.predicate = GEN_PREDICATE_NONE;
sel.curr.noMask = 1;
- sel.MOV(header, GenRegister::ud8grf(0, 0));
+ sel.MOV(header, GenRegister::immud(0));
// Update the header with the coord
sel.curr.execWidth = 1;
@@ -7962,7 +7962,7 @@ extern bool OCL_DEBUGINFO; // first defined by calling
BVAR in program.cpp
sel.curr.execWidth = 8;
sel.curr.predicate = GEN_PREDICATE_NONE;
sel.curr.noMask = 1;
- sel.MOV(header, GenRegister::ud8grf(0, 0));
+ sel.MOV(header, GenRegister::immud(0));
// Update the header with the coord
sel.curr.execWidth = 1;
--
2.7.4
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