Mark Hahn schrieb:
Not quite, this would make no use of two HT channels. Its like
this:
c--c--c--c
| | \/|
| | /\|
c--c--c--c
(The two leftmost CPUs need their third HT to connect the two
chipsets.)
are you sure about that (ie, inspected the traces, or the HT
routing tables)?
Well, as far as the traces are visible they show above connections.
And the Tyan documentation contains a drawing:
ftp://ftp.tyan.com/manuals/m_vx50b4881_100.pdf
(Page 17 of 56)
But be aware, there are other Tyan docs which contain a wrong drawing.
(With a fourth vertical link between nodes 5 and 6. This is not
possible with the limit of three HT links of an Opteron.)
I have not looked at the HT routing tables, how is this possible?
Do you know some program to display them?
by your logic, for instance, a plain 4x would have one
cross-link (and I don't think they do.)
The plain 4x boards I know have a simple ring layout without diagonal
links. (Well, 8 of the 12 available HT links are already in use for the
ring and one or two must go to the chipset(s)...)
Best wishes
Karsten Petersen
--
HPC System Engineer
Tel.: +49 3722 528 43
Fax: +49 3722 528 15
E-Mail: [EMAIL PROTECTED]
MEGWARE Computer GmbH
Vertrieb und Service
Nordstraße 19
09247 Chemnitz/Röhrsdorf
Germany
http://www.megware.com
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