----- "Mikhail Kuzminsky" <[EMAIL PROTECTED]> wrote: > Yes, this AMD errata document says that in B3 revision the error "will > be fixed". I heard that new CPUs w/o TLB+L3 error are shipped now, > but are this CPUs really B3 or may be have some more new release ?
They certainly do exist, we've got 94 nodes of them here and no longer require the kernel patch to work around the errata. -- Christopher Samuel - (03) 9925 4751 - Systems Manager The Victorian Partnership for Advanced Computing P.O. Box 201, Carlton South, VIC 3053, Australia VPAC is a not-for-profit Registered Research Agency _______________________________________________ Beowulf mailing list, [email protected] To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf
