On Wed, Feb 08, 2012 at 02:13:49PM +0100, Peter Kjellström wrote: > * Memory bandwidth to all those FPUs
Memory stacking via TSV is coming. APUs with their very apparent memory bottlenecks will accelerate it. > * Power (CPUs in servers today max out around 120W with GPUs at >250W) I don't see why you can't integrate APU+memory+heatsink in a watercooled module that is plugged into the backplane which contains the switched signalling fabric. > Either way we're in for an interesting future (as usual) :-) I don't see how x86 should make it to exascale. It's too bad MRAM/FeRAM/whatever isn't ready for SoC yet. Also, Moore should end by around 2020 or earlier, and architecture only pushes you one or two generations further at most. Don't see how 3D integration should be ready by then, and 2.5 D only buys you another one or two doublings at best. (TSV stacking is obviously off-Moore). _______________________________________________ Beowulf mailing list, [email protected] sponsored by Penguin Computing To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf
