ChangeSet 1.2199.14.16, 2005/03/23 11:07:37-08:00, [EMAIL PROTECTED]
[TG3]: Add unstable PLL workaround for 5750
Add unstable PLL clock workaround for 5750 Ax and Bx devices. The
workaround
code is run just before entering D3hot state.
Signed-off-by: Michael Chan <[EMAIL PROTECTED]>
ACKed-by: Jeff Garzik <[EMAIL PROTECTED]>
Signed-off-by: David S. Miller <[EMAIL PROTECTED]>
tg3.c | 12 ++++++++++++
1 files changed, 12 insertions(+)
diff -Nru a/drivers/net/tg3.c b/drivers/net/tg3.c
--- a/drivers/net/tg3.c 2005-03-26 17:21:05 -08:00
+++ b/drivers/net/tg3.c 2005-03-26 17:21:05 -08:00
@@ -966,6 +966,7 @@
#define RESET_KIND_SUSPEND 2
static void tg3_write_sig_post_reset(struct tg3 *, int);
+static int tg3_halt_cpu(struct tg3 *, u32);
static int tg3_set_power_state(struct tg3 *tp, int state)
{
@@ -1123,6 +1124,17 @@
}
tg3_frob_aux_power(tp);
+
+ /* Workaround for unstable PLL clock */
+ if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+ u32 val = tr32(0x7d00);
+
+ val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+ tw32(0x7d00, val);
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+ tg3_halt_cpu(tp, RX_CPU_BASE);
+ }
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
-
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