ChangeSet 1.2216, 2005/03/30 09:46:17-08:00, [EMAIL PROTECTED]
[PATCH] FRV: Fix TLB miss mapping cache flush
This fixes the TLB miss mapping cache flush function.
The flush was attempting to invalidate the coverage start virtual
addresses
for the cached page table mappings held in registers SCR0 and SCR1 by
writing
0 into them. Unfortunately, 0x00000000-0x04000000 is itself a valid
part of
the virtual address range. This patches places -1 in there instead, thus
specifying 0xfc000000-0xffffffff which is covered by a static I/O
mapping, and
so shouldn't ever be seen by the TLB-miss handler.
Signed-Off-By: David Howells <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
tlbflush.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
diff -Nru a/include/asm-frv/tlbflush.h b/include/asm-frv/tlbflush.h
--- a/include/asm-frv/tlbflush.h 2005-03-30 12:14:29 -08:00
+++ b/include/asm-frv/tlbflush.h 2005-03-30 12:14:29 -08:00
@@ -58,7 +58,8 @@
#define __flush_tlb_global() flush_tlb_all()
#define flush_tlb() flush_tlb_all()
#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-#define flush_tlb_pgtables(mm,start,end) asm volatile("movgs gr0,scr0 !
movgs gr0,scr1");
+#define flush_tlb_pgtables(mm,start,end) \
+ asm volatile("movgs %0,scr0 ! movgs %0,scr1" :: "r"(ULONG_MAX) :
"memory");
#else
-
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