ChangeSet 1.2181.2.49, 2005/03/26 19:31:26-08:00, [EMAIL PROTECTED]
[SPARC64]: Create and use new macro, DCACHE_ALIASING_POSSIBLE.
It determines whether D-cache aliasing issues are
possible, and if not elide all of the D-cache flushing
code and logic.
Signed-off-by: David S. Miller <[EMAIL PROTECTED]>
arch/sparc64/kernel/smp.c | 9 ++++++++-
arch/sparc64/kernel/sparc64_ksyms.c | 3 +++
arch/sparc64/mm/init.c | 10 ++++++----
arch/sparc64/mm/ultra.S | 26 ++++++++++++++++----------
include/asm-sparc64/cacheflush.h | 17 +++++++++++++++--
include/asm-sparc64/ide.h | 10 +++++-----
include/asm-sparc64/pgalloc.h | 3 ++-
7 files changed, 55 insertions(+), 23 deletions(-)
diff -Nru a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
--- a/arch/sparc64/kernel/smp.c 2005-04-03 21:13:30 -07:00
+++ b/arch/sparc64/kernel/smp.c 2005-04-03 21:13:30 -07:00
@@ -627,7 +627,10 @@
extern unsigned long xcall_flush_tlb_all_cheetah;
extern unsigned long xcall_report_regs;
extern unsigned long xcall_receive_signal;
+
+#ifdef DCACHE_ALIASING_POSSIBLE
extern unsigned long xcall_flush_dcache_page_cheetah;
+#endif
extern unsigned long xcall_flush_dcache_page_spitfire;
#ifdef CONFIG_DEBUG_DCFLUSH
@@ -637,7 +640,7 @@
static __inline__ void __local_flush_dcache_page(struct page *page)
{
-#if (L1DCACHE_SIZE > PAGE_SIZE)
+#ifdef DCACHE_ALIASING_POSSIBLE
__flush_dcache_page(page_address(page),
((tlb_type == spitfire) &&
page_mapping(page) != NULL));
@@ -672,11 +675,13 @@
(u64) pg_addr,
mask);
} else {
+#ifdef DCACHE_ALIASING_POSSIBLE
data0 =
((u64)&xcall_flush_dcache_page_cheetah);
cheetah_xcall_deliver(data0,
__pa(pg_addr),
0, mask);
+#endif
}
#ifdef CONFIG_DEBUG_DCFLUSH
atomic_inc(&dcpage_flushes_xcall);
@@ -709,10 +714,12 @@
(u64) pg_addr,
mask);
} else {
+#ifdef DCACHE_ALIASING_POSSIBLE
data0 = ((u64)&xcall_flush_dcache_page_cheetah);
cheetah_xcall_deliver(data0,
__pa(pg_addr),
0, mask);
+#endif
}
#ifdef CONFIG_DEBUG_DCFLUSH
atomic_inc(&dcpage_flushes_xcall);
diff -Nru a/arch/sparc64/kernel/sparc64_ksyms.c
b/arch/sparc64/kernel/sparc64_ksyms.c
--- a/arch/sparc64/kernel/sparc64_ksyms.c 2005-04-03 21:13:30 -07:00
+++ b/arch/sparc64/kernel/sparc64_ksyms.c 2005-04-03 21:13:30 -07:00
@@ -216,8 +216,11 @@
EXPORT_SYMBOL(tlb_type);
EXPORT_SYMBOL(get_fb_unmapped_area);
EXPORT_SYMBOL(flush_icache_range);
+
EXPORT_SYMBOL(flush_dcache_page);
+#ifdef DCACHE_ALIASING_POSSIBLE
EXPORT_SYMBOL(__flush_dcache_range);
+#endif
EXPORT_SYMBOL(mostek_lock);
EXPORT_SYMBOL(mstk48t02_regs);
diff -Nru a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
--- a/arch/sparc64/mm/init.c 2005-04-03 21:13:30 -07:00
+++ b/arch/sparc64/mm/init.c 2005-04-03 21:13:30 -07:00
@@ -135,7 +135,7 @@
atomic_inc(&dcpage_flushes);
#endif
-#if (L1DCACHE_SIZE > PAGE_SIZE)
+#ifdef DCACHE_ALIASING_POSSIBLE
__flush_dcache_page(page_address(page),
((tlb_type == spitfire) &&
page_mapping(page) != NULL));
@@ -947,6 +947,7 @@
}
}
+#ifdef DCACHE_ALIASING_POSSIBLE
void __flush_dcache_range(unsigned long start, unsigned long end)
{
unsigned long va;
@@ -970,6 +971,7 @@
"i" (ASI_DCACHE_INVALIDATE));
}
}
+#endif /* DCACHE_ALIASING_POSSIBLE */
/* If not locked, zap it. */
void __flush_tlb_all(void)
@@ -1087,7 +1089,7 @@
* using the later address range, accesses with the first address
* range will see the newly initialized data rather than the garbage.
*/
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing
problem */
+#ifdef DCACHE_ALIASING_POSSIBLE
#define DC_ALIAS_SHIFT 1
#else
#define DC_ALIAS_SHIFT 0
@@ -1111,7 +1113,7 @@
unsigned long paddr;
pte_t *pte;
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing
problem */
+#ifdef DCACHE_ALIASING_POSSIBLE
set_page_count(page, 1);
ClearPageCompound(page);
@@ -1129,7 +1131,7 @@
to_free = (unsigned long *) paddr;
}
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing
problem */
+#ifdef DCACHE_ALIASING_POSSIBLE
/* Now free the other one up, adjust cache size. */
preempt_disable();
*to_free = (unsigned long) pte_quicklist[color ^ 0x1];
diff -Nru a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
--- a/arch/sparc64/mm/ultra.S 2005-04-03 21:13:30 -07:00
+++ b/arch/sparc64/mm/ultra.S 2005-04-03 21:13:30 -07:00
@@ -13,6 +13,7 @@
#include <asm/pil.h>
#include <asm/head.h>
#include <asm/thread_info.h>
+#include <asm/cacheflush.h>
/* Basically, most of the Spitfire vs. Cheetah madness
* has to do with the fact that Cheetah does not support
@@ -127,16 +128,14 @@
retl
nop
-#if (PAGE_SHIFT == 13)
-#define DTAG_MASK 0x3
-#elif (PAGE_SHIFT == 16)
-#define DTAG_MASK 0x1f
-#elif (PAGE_SHIFT == 19)
-#define DTAG_MASK 0xff
-#elif (PAGE_SHIFT == 22)
-#define DTAG_MASK 0x3ff
+#ifdef DCACHE_ALIASING_POSSIBLE
+
+#if (PAGE_SHIFT != 13)
+#error only page shift of 13 is supported by dcache flush
#endif
+#define DTAG_MASK 0x3
+
.align 64
.globl __flush_dcache_page
__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
@@ -193,6 +192,7 @@
membar #Sync
ba,pt %xcc, 2b
nop
+#endif /* DCACHE_ALIASING_POSSIBLE */
.align 32
__prefill_dtlb:
@@ -266,6 +266,7 @@
retl
wrpr %g7, 0x0, %pstate
+#ifdef DCACHE_ALIASING_POSSIBLE
flush_dcpage_cheetah: /* 11 insns */
sethi %uhi(PAGE_OFFSET), %g1
sllx %g1, 32, %g1
@@ -278,6 +279,7 @@
nop
retl /* I-cache flush never needed on Cheetah, see callers.
*/
nop
+#endif /* DCACHE_ALIASING_POSSIBLE */
cheetah_patch_one:
1: lduw [%o1], %g1
@@ -308,12 +310,14 @@
call cheetah_patch_one
mov 22, %o2
+#ifdef DCACHE_ALIASING_POSSIBLE
sethi %hi(__flush_dcache_page), %o0
or %o0, %lo(__flush_dcache_page), %o0
sethi %hi(flush_dcpage_cheetah), %o1
or %o1, %lo(flush_dcpage_cheetah), %o1
call cheetah_patch_one
mov 11, %o2
+#endif /* DCACHE_ALIASING_POSSIBLE */
ret
restore
@@ -429,6 +433,7 @@
b rtrap_xcall
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
+#ifdef DCACHE_ALIASING_POSSIBLE
.align 32
.globl xcall_flush_dcache_page_cheetah
xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
@@ -440,12 +445,13 @@
nop
retry
nop
+#endif /* DCACHE_ALIASING_POSSIBLE */
.globl xcall_flush_dcache_page_spitfire
xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
%g7 == kernel page virtual address
%g5 == (page->mapping != NULL) */
-#if (L1DCACHE_SIZE > PAGE_SIZE)
+#ifdef DCACHE_ALIASING_POSSIBLE
srlx %g1, (13 - 2), %g1 ! Form tag comparitor
sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
sub %g3, (1 << 5), %g3 ! D$ linesize == 32
@@ -464,7 +470,7 @@
sub %g3, (1 << 5), %g3
brz,pn %g5, 2f
-#endif /* L1DCACHE_SIZE > PAGE_SIZE */
+#endif /* DCACHE_ALIASING_POSSIBLE */
sethi %hi(PAGE_SIZE), %g3
1: flush %g7
diff -Nru a/include/asm-sparc64/cacheflush.h b/include/asm-sparc64/cacheflush.h
--- a/include/asm-sparc64/cacheflush.h 2005-04-03 21:13:30 -07:00
+++ b/include/asm-sparc64/cacheflush.h 2005-04-03 21:13:30 -07:00
@@ -2,6 +2,17 @@
#define _SPARC64_CACHEFLUSH_H
#include <linux/config.h>
+#include <asm/page.h>
+
+/* Flushing for D-cache alias handling is only needed if
+ * the page size is smaller than 16K.
+ */
+#if PAGE_SHIFT < 14
+#define DCACHE_ALIASING_POSSIBLE
+#endif
+
+#ifndef __ASSEMBLY__
+
#include <linux/mm.h>
/* Cache flush operations. */
@@ -20,9 +31,9 @@
* module load, so we need this.
*/
extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void __flush_icache_page(unsigned long);
extern void __flush_dcache_page(void *addr, int flush_icache);
-extern void __flush_icache_page(unsigned long);
extern void flush_dcache_page_impl(struct page *page);
#ifdef CONFIG_SMP
extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
@@ -33,6 +44,7 @@
#endif
extern void __flush_dcache_range(unsigned long start, unsigned long end);
+extern void flush_dcache_page(struct page *page);
#define flush_icache_page(vma, pg) do { } while(0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
@@ -49,11 +61,12 @@
memcpy(dst, src, len); \
} while (0)
-extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
+
+#endif /* !__ASSEMBLY__ */
#endif /* _SPARC64_CACHEFLUSH_H */
diff -Nru a/include/asm-sparc64/ide.h b/include/asm-sparc64/ide.h
--- a/include/asm-sparc64/ide.h 2005-04-03 21:13:30 -07:00
+++ b/include/asm-sparc64/ide.h 2005-04-03 21:13:30 -07:00
@@ -13,8 +13,8 @@
#include <linux/config.h>
#include <asm/pgalloc.h>
#include <asm/io.h>
-#include <asm/page.h>
#include <asm/spitfire.h>
+#include <asm/cacheflush.h>
#ifndef MAX_HWIFS
# ifdef CONFIG_BLK_DEV_IDEPCI
@@ -51,7 +51,7 @@
static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
{
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem
*/
+#ifdef DCACHE_ALIASING_POSSIBLE
unsigned long end = (unsigned long)dst + (count << 1);
#endif
u16 *ps = dst;
@@ -74,7 +74,7 @@
if(count)
*ps++ = inw_be(port);
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem
*/
+#ifdef DCACHE_ALIASING_POSSIBLE
__flush_dcache_range((unsigned long)dst, end);
#endif
}
@@ -88,7 +88,7 @@
static inline void __ide_outsw(void __iomem *port, void *src, u32 count)
{
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem
*/
+#ifdef DCACHE_ALIASING_POSSIBLE
unsigned long end = (unsigned long)src + (count << 1);
#endif
const u16 *ps = src;
@@ -111,7 +111,7 @@
if(count)
outw_be(*ps, port);
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem
*/
+#ifdef DCACHE_ALIASING_POSSIBLE
__flush_dcache_range((unsigned long)src, end);
#endif
}
diff -Nru a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
--- a/include/asm-sparc64/pgalloc.h 2005-04-03 21:13:30 -07:00
+++ b/include/asm-sparc64/pgalloc.h 2005-04-03 21:13:30 -07:00
@@ -11,6 +11,7 @@
#include <asm/spitfire.h>
#include <asm/pgtable.h>
#include <asm/cpudata.h>
+#include <asm/cacheflush.h>
/* Page table allocation/freeing. */
#ifdef CONFIG_SMP
@@ -125,7 +126,7 @@
#endif /* CONFIG_SMP */
-#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing
problem */
+#ifdef DCACHE_ALIASING_POSSIBLE
#define VPTE_COLOR(address) (((address) >> (PAGE_SHIFT + 10)) & 1UL)
#define DCACHE_COLOR(address) (((address) >> PAGE_SHIFT) & 1UL)
#else
-
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