tree 7282c4763f1e929a54986f04a2783a78438dc034
parent 0e288a4904e37d2ce38e0e20192c74dac9efd2f7
author Eugene Surovegin <[EMAIL PROTECTED]> Tue Apr 12 08:24:49 2005
committer Linus Torvalds <[EMAIL PROTECTED]> Tue Apr 12 08:24:49 2005
[PATCH] ppc32: ppc4xx_pic - add acknowledge when enabling level-sensitive IRQ
This patch adds interrupt acknowledge to the PPC4xx PIC enable_irq
implementation for level-sensitive IRQ sources. This helps in cases when
enable/disable_irq is used in interrupt handlers for hardware, which
requires IRQ acknowledge to be issued from non-interrupt context (e.g.
when actual ACK in device needs an I2C transaction). For such strange
hardware, interrupt handler disables IRQ and defers actual ACK to some
other context. When this happens, IRQ is enabled again. For
level-sensitive sources we get spurious triggering right after IRQ is
enabled. This patch fixes this.
Suggested by Tolunay Orkun <[EMAIL PROTECTED]>.
Signed-off-by: Eugene Surovegin <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
ppc4xx_pic.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletion(-)
Index: arch/ppc/syslib/ppc4xx_pic.c
===================================================================
--- 553e4605a88c38a9028e648451d03f21023be098/arch/ppc/syslib/ppc4xx_pic.c
(mode:100644 sha1:e05fea70a56064236d43740f69c05c2bfcbe709b)
+++ 7282c4763f1e929a54986f04a2783a78438dc034/arch/ppc/syslib/ppc4xx_pic.c
(mode:100644 sha1:36e63376b295da1788d88965b027b798f927c5a1)
@@ -41,7 +41,10 @@
#define UIC_HANDLERS(n)
\
static void ppc4xx_uic##n##_enable(unsigned int irq) \
{ \
- ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq); \
+ u32 mask = IRQ_MASK_UIC##n(irq); \
+ if (irq_desc[irq].status & IRQ_LEVEL) \
+ mtdcr(DCRN_UIC_SR(UIC##n), mask); \
+ ppc_cached_irq_mask[n] |= mask; \
mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
} \
\
-
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