tree afff90617361a00535ca52f0e2828998a92495ee
parent c38401e826939fd7d08eb059f99917607518a59f
author Kumar Gala <[EMAIL PROTECTED]> Tue Apr 12 08:24:55 2005
committer Linus Torvalds <[EMAIL PROTECTED]> Tue Apr 12 08:24:55 2005
[PATCH] ppc32: make usage of CONFIG_PTE_64BIT & CONFIG_PHYS_64BIT consistent
CONFIG_PTE_64BIT & CONFIG_PHYS_64BIT are not currently consistently used in
the code base. Fixed up the usage such that CONFIG_PTE_64BIT is used when we
have a 64-bit PTE regardless of physical address width. CONFIG_PHYS_64BIT is
used if the physical address width is larger than 32-bits, regardless of PTE
size.
These changes required a few sub-arch specific ifdef's to be fixed and the
introduction of a physical address format string.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
arch/ppc/mm/pgtable.c | 10 +++++-----
include/asm-ppc/mmu.h | 4 +++-
2 files changed, 8 insertions(+), 6 deletions(-)
Index: arch/ppc/mm/pgtable.c
===================================================================
--- 04cdfe8df85d3085c5564b279c032d379c7fa225/arch/ppc/mm/pgtable.c
(mode:100644 sha1:9146776fb0316ce36815add5b7f54c7089149793)
+++ afff90617361a00535ca52f0e2828998a92495ee/arch/ppc/mm/pgtable.c
(mode:100644 sha1:eee9ab8b994de6c10aa19eac3b9a384c7404bf06)
@@ -74,7 +74,7 @@
#define p_mapped_by_tlbcam(x) (0UL)
#endif /* HAVE_TLBCAM */
-#ifdef CONFIG_44x
+#ifdef CONFIG_PTE_64BIT
/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */
#define PGDIR_ORDER 1
#else
@@ -142,13 +142,13 @@
__free_page(ptepage);
}
-#ifndef CONFIG_44x
+#ifndef CONFIG_PHYS_64BIT
void __iomem *
ioremap(phys_addr_t addr, unsigned long size)
{
return __ioremap(addr, size, _PAGE_NO_CACHE);
}
-#else /* CONFIG_44x */
+#else /* CONFIG_PHYS_64BIT */
void __iomem *
ioremap64(unsigned long long addr, unsigned long size)
{
@@ -162,7 +162,7 @@
return ioremap64(addr64, size);
}
-#endif /* CONFIG_44x */
+#endif /* CONFIG_PHYS_64BIT */
void __iomem *
__ioremap(phys_addr_t addr, unsigned long size, unsigned long flags)
@@ -193,7 +193,7 @@
*/
if ( mem_init_done && (p < virt_to_phys(high_memory)) )
{
- printk("__ioremap(): phys addr "PTE_FMT" is RAM lr %p\n", p,
+ printk("__ioremap(): phys addr "PHYS_FMT" is RAM lr %p\n", p,
__builtin_return_address(0));
return NULL;
}
Index: include/asm-ppc/mmu.h
===================================================================
--- 04cdfe8df85d3085c5564b279c032d379c7fa225/include/asm-ppc/mmu.h
(mode:100644 sha1:1d68d73eff116d6539696137e7ec89fd45e60629)
+++ afff90617361a00535ca52f0e2828998a92495ee/include/asm-ppc/mmu.h
(mode:100644 sha1:c2091fd3fd46d5df2e3e4b98ad80a4873e60ba47)
@@ -15,11 +15,13 @@
* virtual/physical addressing like 32-bit virtual / 36-bit
* physical need a larger than native word size type. -Matt
*/
-#ifndef CONFIG_PTE_64BIT
+#ifndef CONFIG_PHYS_64BIT
typedef unsigned long phys_addr_t;
+#define PHYS_FMT "%.8lx"
#else
typedef unsigned long long phys_addr_t;
extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+#define PHYS_FMT "%16Lx"
#endif
/* Default "unsigned long" context */
-
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