tree bcdd3c61fa4341a20de81dafdfd681d8872f0eb9
parent a757e64cfa400391041ed7953f0290c34a820c93
author Russell King <[EMAIL PROTECTED]> Sun, 17 Apr 2005 15:36:55 +0100
committer Russell King <[EMAIL PROTECTED]> Sun, 17 Apr 2005 15:36:55 +0100
[PATCH] ARM: footbridge rtc init
The footbridge ISA RTC was being initialised before we had setup the
kernel timer. This caused a divide by zero error when the current
time of day is set. Resolve this by initialising the RTC after
the kernel timer has been initialised.
Signed-off-by: Russell King <[EMAIL PROTECTED]>
arm/mach-footbridge/dc21285-timer.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: arch/arm/mach-footbridge/dc21285-timer.c
===================================================================
---
73214a96945eb017e33c0f732ad0f1e8d10c2e8e/arch/arm/mach-footbridge/dc21285-timer.c
(mode:100644 sha1:580e1d4bce081630eae12df54c84955e1b3c2076)
+++
bcdd3c61fa4341a20de81dafdfd681d8872f0eb9/arch/arm/mach-footbridge/dc21285-timer.c
(mode:100644 sha1:da5b9b7623ca9fb6537bc22d26f45aceb4986d24)
@@ -51,8 +51,6 @@
*/
static void __init footbridge_timer_init(void)
{
- isa_rtc_init();
-
timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
*CSR_TIMER1_CLR = 0;
@@ -60,6 +58,8 @@
*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
TIMER_CNTL_DIV16;
setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
+
+ isa_rtc_init();
}
struct sys_timer footbridge_timer = {
-
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