tree 02b2fd5de20468f5966cf3e73fbfa5e6f86baa63
parent 361b4ac29bc651c7612d4bf21434ae6fe06b78e4
author Michael Chan <[EMAIL PROTECTED]> Fri, 22 Apr 2005 07:12:05 -0700
committer David S. Miller <[EMAIL PROTECTED]> Fri, 22 Apr 2005 07:12:05 -0700
[TG3]: Add nvram lock-out support for 5752 TPM
Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out
is enabled, certain NVRAM registers cannot be written to.
Signed-off-by: Michael Chan <[EMAIL PROTECTED]>
Signed-off-by: David S. Miller <[EMAIL PROTECTED]>
net/tg3.c | 70 +++++++++++++++++++++++++++++++-------------------------------
net/tg3.h | 1
2 files changed, 37 insertions(+), 34 deletions(-)
Index: drivers/net/tg3.c
===================================================================
--- a0d1b0a7f89a7d45c63b269bef5eeacf6f8dc734/drivers/net/tg3.c (mode:100644
sha1:dbdd3ecafdc1a003e1a74415f89d88f955d895a1)
+++ 02b2fd5de20468f5966cf3e73fbfa5e6f86baa63/drivers/net/tg3.c (mode:100644
sha1:30154642573644f8c49ca0c39ff7c294f9ec806a)
@@ -3732,6 +3732,28 @@ static void tg3_nvram_unlock(struct tg3
}
/* tp->lock is held. */
+static void tg3_enable_nvram_access(struct tg3 *tp)
+{
+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+ u32 nvaccess = tr32(NVRAM_ACCESS);
+
+ tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+ }
+}
+
+/* tp->lock is held. */
+static void tg3_disable_nvram_access(struct tg3 *tp)
+{
+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+ u32 nvaccess = tr32(NVRAM_ACCESS);
+
+ tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+ }
+}
+
+/* tp->lock is held. */
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
{
if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
@@ -7102,6 +7124,10 @@ static void __devinit tg3_get_5752_nvram
nvcfg1 = tr32(NVRAM_CFG1);
+ /* NVRAM protection for TPM */
+ if (nvcfg1 & (1 << 27))
+ tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
@@ -7179,11 +7205,7 @@ static void __devinit tg3_nvram_init(str
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
tp->tg3_flags |= TG3_FLAG_NVRAM;
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
- }
+ tg3_enable_nvram_access(tp);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tg3_get_5752_nvram_info(tp);
@@ -7192,11 +7214,7 @@ static void __devinit tg3_nvram_init(str
tg3_get_nvram_size(tp);
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
- }
+ tg3_disable_nvram_access(tp);
} else {
tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -7285,11 +7303,7 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_lock(tp);
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
- }
+ tg3_enable_nvram_access(tp);
tw32(NVRAM_ADDR, offset);
ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
@@ -7300,11 +7314,7 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_unlock(tp);
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
- }
+ tg3_disable_nvram_access(tp);
return ret;
}
@@ -7367,7 +7377,7 @@ static int tg3_nvram_write_block_unbuffe
while (len) {
int j;
- u32 phy_addr, page_off, size, nvaccess;
+ u32 phy_addr, page_off, size;
phy_addr = offset & ~pagemask;
@@ -7390,8 +7400,7 @@ static int tg3_nvram_write_block_unbuffe
offset = offset + (pagesize - page_off);
- nvaccess = tr32(NVRAM_ACCESS);
- tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+ tg3_enable_nvram_access(tp);
/*
* Before we can erase the flash page, we need
@@ -7528,13 +7537,10 @@ static int tg3_nvram_write_block(struct
tg3_nvram_lock(tp);
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-
+ tg3_enable_nvram_access(tp);
+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
tw32(NVRAM_WRITE1, 0x406);
- }
grc_mode = tr32(GRC_MODE);
tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
@@ -7553,11 +7559,7 @@ static int tg3_nvram_write_block(struct
grc_mode = tr32(GRC_MODE);
tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
- u32 nvaccess = tr32(NVRAM_ACCESS);
-
- tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
- }
+ tg3_disable_nvram_access(tp);
tg3_nvram_unlock(tp);
}
Index: drivers/net/tg3.h
===================================================================
--- a0d1b0a7f89a7d45c63b269bef5eeacf6f8dc734/drivers/net/tg3.h (mode:100644
sha1:261c2db7ce17c27d71c6e196e6e8a7b4c8d15d05)
+++ 02b2fd5de20468f5966cf3e73fbfa5e6f86baa63/drivers/net/tg3.h (mode:100644
sha1:d3f03f0f4c46dba038884f893b5385ff9c6e9070)
@@ -2122,6 +2122,7 @@ struct tg3 {
#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
#define TG3_FLG2_5705_PLUS 0x00040000
#define TG3_FLG2_5750_PLUS 0x00080000
+#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3
-
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