tree c0f8f7e7e774dd22d74553ce72ae1b8d8127fe39
parent ef4d7cbea773a77b36e732779cab4018ba2c037b
author Andi Kleen <[EMAIL PROTECTED]> Fri, 29 Jul 2005 11:15:35 -0700
committer Linus Torvalds <[EMAIL PROTECTED]> Fri, 29 Jul 2005 11:45:59 -0700
[PATCH] x86_64: Fix some comments in tlbflush.h
Were either outdated or misleading.
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
include/asm-x86_64/tlbflush.h | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask;
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
*/
#ifndef CONFIG_SMP
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struc
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
- /* x86_64 does not keep any page table caches in TLB */
+ /* x86_64 does not keep any page table caches in a software TLB.
+ The CPUs do in their hardware TLBs, but they are handled
+ by the normal TLB flushing algorithms. */
}
#endif /* _X8664_TLBFLUSH_H */
-
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