tree 9e01b08b8aa2e40a80435570f3dab799f7909a35
parent c70f5d6610c601ea2ae4ae4e49f66c80801e895f
author [EMAIL PROTECTED] <[EMAIL PROTECTED]> Sun, 31 Jul 2005 01:25:32 -0700
committer Linus Torvalds <[EMAIL PROTECTED]> Sun, 31 Jul 2005 03:37:50 -0700
[PATCH] x86_64: avoid wasting IRQs patch update
The patch adds boundary check for the MAX_GSI_NUM. Same as the update for
i386, the patch addresses a problem with ACPI SCI IRQ. The patch corrects
the code such that SCI IRQ is skipped and duplicate entry is avoided. The
VIA chipset uses 4-bit IRQ register for internal interrupt routing, and
therefore cannot handle IRQ numbers assigned to its devices. The patch
corrects this problem by allowing PCI IRQs below 16.
Signed-off-by: Natalie Protasevich <[EMAIL PROTECTED]>
Acked-by: Andi Kleen <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
arch/x86_64/kernel/mpparse.c | 17 +++++++++++++++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -970,8 +970,21 @@ int mp_register_gsi(u32 gsi, int edge_le
* due to unused I/O APIC pins.
*/
int irq = gsi;
- gsi = pci_irq++;
- gsi_to_irq[irq] = gsi;
+ if (gsi < MAX_GSI_NUM) {
+ if (gsi > 15)
+ gsi = pci_irq++;
+#ifdef CONFIG_ACPI_BUS
+ /*
+ * Don't assign IRQ used by ACPI SCI
+ */
+ if (gsi == acpi_fadt.sci_int)
+ gsi = pci_irq++;
+#endif
+ gsi_to_irq[irq] = gsi;
+ } else {
+ printk(KERN_ERR "GSI %u is too high\n", gsi);
+ return gsi;
+ }
}
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
-
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