This paper has everything I like in it - working code, test data, and scripts... and a working hardware implementation:
http://cseweb.ucsd.edu/~ssradhak/Papers/senic-nsdi14.pdf http://jvimal.github.io/senic/ Presented at USENIX last week: "We implemented SENIC on NetFPGA, with 1000 rate limiters requiring just 30KB SRAM, and it was able to accurately pace packets. Further, in a memcached benchmark against software rate limiters, SENIC is able to sustain up to 250% higher load, while simultaneously keeping tail latency under 4ms at 90% network utilization." -- Dave Täht _______________________________________________ Bloat mailing list [email protected] https://lists.bufferbloat.net/listinfo/bloat
